Patents Assigned to TSMC-Acer Semiconductor Manufacturing Corp.
  • Patent number: 6319762
    Abstract: A method for fabricating poly-spacers used in a semiconductor substrate, comprising: forming an undoped first polysilicon layer on the semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; forming a second polysilicon layer on the first polysilicon layer; and etching the first polysilicon layer and the second polysilicon layer to form spacers.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: November 20, 2001
    Assignee: TSMC-ACER Semiconductor Manufacturing Corp.
    Inventors: Shiou-han Liaw, Yau-feng Lo, Po-lung Chuang, Jia-ren Chen, Yen-hung Lai, Calvin Wu
  • Patent number: 6303417
    Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of LPD oxide trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. Finally, the standard processes can be employed for fabricating the CMOS transistors on the substrate.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 16, 2001
    Assignee: TSMC-Acer Semiconductor Manufacturing Corp.
    Inventor: Shye-Lin Wu
  • Patent number: 6281542
    Abstract: A structure of a capacitor on a semiconductor wafer including the following structure is disclosed herein. A first electrode including a flower structure is formed on the semiconductor wafer. The first electrode includes a flower neck portion, a flower bottom portion, and a flower top portion. The flower neck portion is electrically coupled to the semiconductor wafer. The flower bottom portion is electrically coupled to the flower neck portion, in which the flower bottom portion includes a first protudent portion. The flower top portion includes a downward hemispherical portion and a second protrudent portion, and is electrically coupled to the flower neck portion. The flower bottom portion is formed of titanium nitride, and the flower top portion is formed of Ti/TiN or TiW. A first dielectric film is formed on the first electrode, and the first dielectric layer is the dielectric layer of the capacitor. A second electrode is formed on the first dielectric film.
    Type: Grant
    Filed: February 15, 1999
    Date of Patent: August 28, 2001
    Assignee: TSMC-Acer Semiconductor Manufacturing Corp.
    Inventor: Shye-Lin Wu