Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A semiconductor device includes a substrate, a deep well, a doped region, a gate, and source and drain regions. The deep well is of a first conductivity type in the substrate. The doped region is in the deep well with an impurity of a second conductivity type. The field oxide is over the deep well and has a side interfaced with the doped region. The gate is over the field oxide. The source and drain regions are over the substrate and laterally separated at least in part by the doped region and the field oxide.

Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

Abstract: An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. A thermal substrate contact increases the ability to remove heat produced from the integrated circuit transistors out of the integrated circuit. A thermal substrate contact which traverses the oxide layer over a substrate provides a secondary path for heat out of an integrated circuit (or, alternatively, out of a substrate through the integrated circuit) to cool the integrated circuit.

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Abstract: An integrated circuit includes a drift region in a substrate, a drain in the substrate which includes a doped drain well, the doped drain well including a first zone, having a first concentration of a first dopant, and a second zone, having a second concentration of the first dopant, where the first concentration is smaller than the second concentration, and a gate electrode over the drift region and being separated from the doped drain well in a direction parallel to a top surface of the substrate by a distance greater than 0.

Abstract: An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region. The first gate has a first portion extending along a first direction and a second portion extending along a second direction. The second gate has a first portion extending along the first direction and a second portion extending along the second direction. The shared drain region extends from the first portion of the first gate to the first portion of the second gate. The first source region is spaced apart from the shared drain region by the first gate. The second source region is spaced apart from the shared drain region by the second gate. The isolation region is between the first portion of the first gate and the first portion of the second gate, and resembles a quadrilateral pattern bordering the shared drain region.

Abstract: An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Abstract: A semiconductor device includes a doped region of a first conductivity type in a substrate, a source/drain region of the first conductivity in the doped region, and a gate structure overlapping a portion of the doped region. The semiconductor device further comprises a multi-layer spacer over a first sidewall of the gate structure. The multi-layer spacer comprises a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer. The first spacer layer and the second spacer layer are in contact with the first sidewall of the gate structure.

Abstract: A method includes: turning on a first switch coupled between a first array of memory and a voltage supply according to a first charge signal; turning on a second switch coupled between a second array of memory and the voltage supply according to a second charge signal different from the first charge signal; and generating the first charge signal and the second charge signal according to a word line address. The second array of memory is located between the second switch and the first array of memory.

Abstract: A semiconductor device includes a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and having a tip corner in a position substantially level with a top surface of the semiconductor substrate. The gate structure is on the field oxide and laterally extends past the tip corner of the field oxide. The p-type doped region is in the deep n-well and is interfaced with the tip corner of the field oxide. The source region and a drain region are laterally separated at least in part by the p-type doped region and the field oxide.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.

Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

Abstract: A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.

Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Abstract: An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.