Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.

Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

Abstract: An integrated circuit is provided and includes a first active region of a first conductivity type coupled to a first voltage terminal and corresponding to a first terminal of a first transistor and a first terminal of a second transistor included in an inverter of a level shifter circuit, wherein the first transistor is configured to discharge electrostatic charges to the first voltage terminal; and second and third active regions, corresponding to a third transistor, of a second conductivity type different from the first conductivity type, wherein the second active region is coupled to a second voltage terminal, and the third active region is coupled to a first terminal, different from the second voltage terminal, of the level shifter circuit. The third transistor is configured to transmit a first supply voltage from the second voltage terminal for the integrated circuit.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Abstract: A semiconductor device includes a source region, a drain region, a gate structure, a first gate spacer, and a second gate spacer. The source region and the drain region are in a substrate. The gate structure is laterally between the source region and the drain region. The first gate spacer is on a first sidewall of the gate structure. The second gate spacer is on a second sidewall of the gate structure. The first gate spacer has more layers than the second gate spacer.

Abstract: An organic light emitting diode display includes an integrated circuit, a first electrode, a spacer, an organic material stack layer, and a second electrode. The first electrode is electrically connected to the integrated circuit and has a top surface, a bottom surface, and an inclined surface connecting the top and bottom surfaces. An angle between the inclined surface and the bottom surface is in a range from about 45 degrees to about 80 degrees. The spacer is disposed to cover the inclined surface of the first electrode. The organic material stack layer is disposed on the first electrode. The second electrode is disposed on the organic material stack layer and the spacers.

Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

Abstract: A method includes forming a bottom electrode of a capacitor over a substrate; depositing an isolation dielectric layer of the capacitor over the bottom electrode; and forming a top electrode of the capacitor over the isolation dielectric layer. Depositing the isolation dielectric layer includes heating the substrate to a predetermined temperature range; depositing a first sub-layer of the isolation dielectric layer at the predetermined temperature range; cooling down the substrate and the first sub-layer; heating the substrate and the first sub-layer to the predetermined temperature range; and depositing a second sub-layer of the isolation dielectric layer on the first sub-layer at the predetermined temperature range. Cooling down the substrate and the first sub-layer and heating the substrate and the first sub-layer are performed under an vacuum condition without vacuum break therebetween.

Abstract: A method of making an integrated circuit includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type. The drain well includes a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant. The method further includes forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well being adjacent to the drift region in the substrate. The method includes forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well. The method includes forming a drain low-density doped (LDD) region in the second zone of the drain well.

Abstract: A method of manufacturing an IC structure includes forming first through fourth PMOS transistors in an n-well, constructing a bias circuit including the first and second PMOS transistors, constructing a level shifter including the third and fourth PMOS transistors, building a first power distribution structure including electrical connections to each of the first and third PMOS transistors, and building a second power distribution structure including electrical connections to each of the second and fourth PMOS transistors.

Abstract: An integrated circuit includes a substrate and a semiconductor material layer over the substrate. The integrated circuit includes a first source structure in the semiconductor material layer. The first source structure includes a first doped well. The integrated circuit includes a drain structure in the semiconductor material layer. The drain structure includes a second doped well. The integrated circuit includes a second source structure in the semiconductor material layer. The second source structure includes a third doped well. The drain structure is between the first source structure and the second source structure. The integrated circuit includes a first deep trench isolation (DTI) extending through the first doped well; and a first thermal contact extending through the first DTI. The thermal contact is in direct contact with the substrate. The first DTI is between the thermal contact and the first doped well.

Abstract: A circuit (to shape a follower voltage for a follower circuit) includes a tie-low circuit and an anti-noise circuit. The tie-low circuit is connected between a follower node and a first reference voltage. The tie-low circuit is responsive to a second reference voltage. The follower node is connectable to the follower circuit. The anti-noise circuit is connected between the follower node and the second reference voltage. The anti-noise circuit is configured to protect the follower voltage at the follower node from otherwise being distorted by a noise voltage being coupled capacitively to the follower node.

Abstract: A system includes at least one sensor and at least one controller. The at least one sensor is configured to generate a first weight signal corresponding to a first weight of a first lot of substrates, and a second weight signal corresponding to a second weight of a second lot of substrates. The at least one controller is coupled to the at least one sensor to receive the first weight signal and the second weight signal. The at least one controller is configured to convert a weight difference between the first weight and the second weight into a number of substrates each having a predetermined weight. The at least one controller is further configured to, based on the converted number of substrates, control a processing apparatus to rotate the first lot of substrates and the second lot of substrates simultaneously.