Patents Assigned to TTPCOM Limited
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Patent number: 8095094Abstract: A communication semiconductor integrated circuit includes a phase control loop and an amplitude control loop. A gain of a variable gain amplifier when it is detected from an output of the comparator that the amplitudes of the reference signal and the feedback signal are equal to each other while a predetermined DC voltage is applied to an amplifier which amplifies an output of a transmission oscillation circuit and is controlled by the amplitude control loop to vary the gain of the variable gain amplifier on a feedback path is held in a register. Thereafter, the DC voltage is changed to another value to detect the gain of the variable gain amplifier, so that the gain of a variable gain amplifier on the forward path is decided on the basis of the detected gain and the gain held in the register.Type: GrantFiled: November 3, 2008Date of Patent: January 10, 2012Assignees: Renesas Electronics Corporation, TTPCOM LimitedInventors: Hiroaki Matsui, Taizo Yamawaki, Yoshiaki Harasawa, Steve Williams
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Publication number: 20110092175Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicants: RENESAS TECHNOLOGY CORP., TTPCOM LIMITEDInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Patent number: 7885626Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: March 27, 2008Date of Patent: February 8, 2011Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20090129445Abstract: A method of evaluating the usage in a received signal of codes from a tree of codes that can be used to orthogonalise communications signals, the method including testing to determine if a given code is in use in the received signal and deducing from the result and from the tree structure the need to test in the received signal for the use of the codes in the portion of the tree depending from said given code. The invention also includes corresponding apparatus and software.Type: ApplicationFiled: November 30, 2005Publication date: May 21, 2009Applicant: TTPCOM LIMITEDInventor: Juha Olavi Korhonen
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Patent number: 7504903Abstract: In a communication semiconductor integrated circuit device, an oscillator of a PLL circuit can operate in a plurality of frequency bands. With a control voltage (Vc) of the oscillator fixed to a predetermined value (VDC), an oscillation frequency of the oscillator is measured for each band to be stored in a storage. When the PLL operates, a setting value to specify a band is compared with the measured frequency values stored in the storage. As a result of the comparison, a band to be actually used by the oscillator is determined.Type: GrantFiled: November 6, 2006Date of Patent: March 17, 2009Assignees: Renesas Technology Corp., TTPCom LimitedInventors: Masumi Kasahara, Hirotaka Osawa, Robert Astle Henshaw
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Patent number: 7499689Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.Type: GrantFiled: March 26, 2007Date of Patent: March 3, 2009Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Astel Henshaw
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Patent number: 7480345Abstract: In a polar loop based radio-communications apparatus having a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmission, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplification circuit, the phase control loop is first started while maintaining the amplitude control loop in an off state at the outset of transmission, and the amplitude control loop is started after stabilizing the phase control loop.Type: GrantFiled: May 2, 2007Date of Patent: January 20, 2009Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Noriyuki Kurakami, Patrick Wurm, Robert Astle Henshaw, David Freeborough
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Patent number: 7463876Abstract: A communication semiconductor integrated circuit includes a phase control loop and an amplitude control loop. A gain of a variable gain amplifier when it is detected from an output of the comparator that the amplitudes of the reference signal and the feedback signal are equal to each other while a predetermined DC voltage is applied to an amplifier which amplifies an output of a transmission oscillation circuit and is controlled by the amplitude control loop to vary the gain of the variable gain amplifier on a feedback path is held in a register. Thereafter, the DC voltage is changed to another value to detect the gain of the variable gain amplifier, so that the gain of a variable gain amplifier on the forward path is decided on the basis of the detected gain and the gain held in the register.Type: GrantFiled: March 9, 2006Date of Patent: December 9, 2008Assignees: Renesas Technolog Corp., TTPCOM LimitedInventors: Hiroaki Matsui, Taizo Yamawaki, Yoshiaki Harasawa, Steve Williams
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Patent number: 7433653Abstract: A transmitter adopting a polar loop system including a phase control loop for controlling the phase of a carrier signal outputted from a transmitting oscillator and an amplitude control loop for controlling the amplitude of a transmitting output signal outputted from a power amplification circuit, and designed to be capable of performing transmission using a GMSK modulation mode and transmission using an 8-PSK modulation mode. In the transmitter, the phase control loop is shared as a phase control loop for use in the GMSK modulation mode and a phase control loop for use in the 8-PSK modulation mode. A component similar to any one of components constituting a loop filter is provided in parallel therewith so that the component can be connected or disconnected in accordance with the modulation mode, for example, by use of a switching element.Type: GrantFiled: June 18, 2007Date of Patent: October 7, 2008Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Ryoichi Takano, Kazuhiko Hikasa, Yasuyuki Kimura, Hiroshi Hagisawa, Patrick Wurm, Robert Astle Henshaw, David Freeborough
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Patent number: 7424276Abstract: In a transmitter of polar-loop architecture having a phase control loop and an amplitude control loop, as loop filters for controlling a loop band of the amplitude control loop, a first filter with lag-lead characteristics (secondary or more filter including a capacitor and a resistor) and a second filter of a perfect integrator type (filter including only a capacitor) are employed, and current-output type circuits are connected to respective front stages of the first and second filters.Type: GrantFiled: February 18, 2003Date of Patent: September 9, 2008Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Taizo Yamawaki, Hisayoshi Kajiwara, Ryoichi Takano, Patrick Wurm
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Publication number: 20080192862Abstract: A scheme for deducing a DC offset in a received signal burst acquired through a particular channel, wherein the received signal burst corresponds to a transmitted signal burst. An impulse response estimate of the channel is used to model how a known or recovered part of the transmitted burst would have been affected by passage through said channel in place of the corresponding part of the transmitted signal burst. The modeled part of the transmitted burst is then compared with the corresponding part of the received signal burst to deduce a DC offset present in the received signal burst.Type: ApplicationFiled: August 15, 2005Publication date: August 14, 2008Applicant: TTPCOM LIMITEDInventors: Manuel Segovia-Martinez, Navid Fatemi-Ghomi, Cyril Valadon
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Publication number: 20080195785Abstract: An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer operating system (5); the interrupt controller being adapted to recognize critical (11) and non-critical (12) interrupt requests originating from different interrupt sources, and to recognize when the processor (7) is required to execute each of critical (3) and non-critical tasks (17); the interrupt controller being further adapted to pass critical interrupt requests (11) to the processor (7) for execution in preference to non-critical interrupt requests (12), to block non-critical interrupt requests (12) to the processor when they coexist with critical interrupt requests (11) or the processor (7) is required to execute critical tasks (3), and to pass non-critical interrupt requests (12) to the processor (7) when they do not coexist with any critical interrupt requests (11)Type: ApplicationFiled: October 17, 2005Publication date: August 14, 2008Applicant: TTPCOM LIMITEDInventor: Eugene Pascal Herczog
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Patent number: 7386064Abstract: In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.Type: GrantFiled: November 6, 2002Date of Patent: June 10, 2008Assignees: Renesas Technology Corp., TTPCOM Limited, Hitachi Advanced Digital, Inc., Hitachi ULSI Systems Co., Ltd.Inventors: Koichi Yahagi, Ryoji Furuya, Fumiaki Matsuzaki, Robert Astle Henshaw
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Patent number: 7366489Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: December 23, 2003Date of Patent: April 29, 2008Assignees: TTPCOM Limited, Renesas Technology Corp.Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Patent number: 7333779Abstract: In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.Type: GrantFiled: May 4, 2005Date of Patent: February 19, 2008Assignees: Renesas Technology Corp., TTPCom LimitedInventors: Taizo Yamawaki, Takefumi Endo, Kazuo Watanabe, Kazuaki Hori, Julian Hildersley
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Patent number: 7324787Abstract: In a radio communication system having a phase control loop for phase modulation and an amplitude control loop for amplitude modulation and being capable of time divisional transmission and reception under a predetermined time management, when transmission in a first mode is switched to transmission in a second mode or when transmission in the second mode is switched to transmission in the first mode, the output level of the power amplifier is lowered once to a predetermined level higher than the level when transmission related circuits are activated, and thereafter the output level of the power amplifier is again ramped after the settings have been changed but without starting of a transmission oscillator, establishing of the phase control loop and the amplitude control loop.Type: GrantFiled: July 29, 2004Date of Patent: January 29, 2008Assignees: Renesas Technology Corporation, TTPCOM LimitedInventors: Noriyuki Kurakami, Kazuhiko Hikasa, Ryoichi Takano, Patrick Wurm
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Patent number: 7313369Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.Type: GrantFiled: May 5, 2005Date of Patent: December 25, 2007Assignees: Renesas Technology Corp., TTPcom LimitedInventors: Hirotaka Oosawa, Jiro Shinbo, Noriyuki Kurakami, Masumi Kasahara, Robert Astle Henshaw
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Publication number: 20070294044Abstract: A method is provided of characterising a data stream of binary symbols, the method comprising sampling the stream at a predetermined rate sufficient to capture at least two samples per binary symbol, identifying the shortest continuous run of samples having the same logic level and assigning a symbol rate to the stream on the basis that the identified run is one symbol in length.Type: ApplicationFiled: July 1, 2005Publication date: December 20, 2007Applicant: TTPCOM LIMITEDInventor: Richard Hunt
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Patent number: 7230997Abstract: In a polar loop based radio-communications apparatus having a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmission, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplification circuit, the phase control loop is first started while maintaining the amplitude control loop in an off state at the outset of transmission, and the amplitude control loop is started after stabilizing the phase control loop.Type: GrantFiled: February 26, 2003Date of Patent: June 12, 2007Assignees: Hitachi, Ltd., TTPCom LimitedInventors: Noriyuki Kurakami, Patrick Wurm, Robert Astle Henshaw, David Freeborough
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Patent number: 7231235Abstract: The audio input system (6) of a terminal, such as a mobile telephone, is powered up during the standby mode, either with the paging channel or any other short duration channel such as a monitoring channel, and is then used to recognize narrow bandwidth sounds such as a whistle, to activate the telephone. Once activated, the telephone may then be responsive to voice commands and may then support a speaker phone mode of application.Type: GrantFiled: April 3, 2003Date of Patent: June 12, 2007Assignee: TTPCom LimitedInventor: William Basil Harrold