Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.

Abstract: A system and method is provided for traffic management and regulation in a packet-based communication network, the system and method facilitating proactive, discriminating congestion control on a per flow basis of packets traversing the Internet via use of a Weighted Random Early Detection (WRED) algorithm that monitors the incoming packet queue and optimizes enqueuing or discard of incoming packets to stabilize queue length and promote efficient packet processing. During optimized discard conditions, the system and method discern a relative priority among incoming packets, distribute packets with a relatively high priority and discard packets with a relatively low priority. Additionally, packet traffic are policed and discarded according to packet type, quantity or other predetermined criteria. The present invention performs in periodic mode, demand mode or both, and can be implemented as a hardware solution, a software solution, or a combination thereof.

Abstract: A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pass gates, one pass gate designated for each MAC port. That is, a switch router is implemented using the multi-port memory array such that the number of ports in each memory cell is proportional to the number of MACs integrated in the single monolithic chip. An arbitrator arbitrates between the integrated ports, a lookup table identifies the destination port and a system controller controls all of the integrated elements.

Abstract: A packet switching system comprises a first switch and a second switch. The first switch includes a first receive port, a first plurality of transmit ports, a first switch fabric, a first reference clock signal input and a first multicast control symbol input/output port coupled to the first plurality of transmit ports for inputting a multicast control signal to be transmitted. The second switch includes a second receive port, a second plurality of transmit ports a second switch fabric, a second reference clock signal input and a second multicast control symbol input/output port coupled to the second receive port for outputting a received multicast control symbol. In operation, a multicast control symbol is generated in hardware synchronized with a reference clock signal and the multicast control symbol directly to the first plurality of transmit ports.

Abstract: A switch for broadcasting packets is provided including a plurality of input ports, a switch fabric coupled to the input ports, a plurality of output ports coupled to the suited fabrics and a multicast interconnect coupled between the input ports and output ports for routing multicast packets directly between the input and output ports. The multicast interconnect may include a multicast queue, an arbiter coupled between the multicast queue and the input ports and a plurality of broadcast buffers coupled to the multicast queue, each broadcast buffer coupled to a corresponding output port. The multicast interconnect may include a plurality of egress arbiters coupled between corresponding broadcast buffers and output ports.

Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.

Abstract: A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.

Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.

Abstract: The present invention provides a digital signal processor (DSP) to peripheral component interconnect (PCI) bus interface/bridging system. The system includes an intermediate bus; a bridge module that is coupled between the PCI bus and the intermediate bus. The bridge module includes a PCI interface and an intermediate bus interface and an IDMA channel coupled between the PCI interface and the intermediate bus interface. A control module is coupled between the bridge module and the DSP circuit, said control module having an intermediate bus control circuit and a DSP control circuit having a slave port controller coupled to the slave port (HPI) of the DSP and a master port controller coupled to the master port (EMIF) of the DSP circuit, whereby the master port continues to transfer data from the DSP circuit to the PCI bus when an additional master circuit is asserted on the PCI bus. The system provides a direct connect solution that also provides arbitration for multiple DSPs.