Abstract: A self-decoding charge pump for charging conductive lines (word lines or bit lines) of a semiconductor programmable memory array such as an EEPROM includes: oscillator output capacitive coupling circuitry connecting an oscillator output to a first control node corresponding to a selected conductive line, for capacitively coupling voltage pulses from the oscillator output to the first control node while the conductive line is selected; control selective charge transfer circuitry connecting a high voltage source to a second control node through the first control node, for selectively transferring charge increments from the high-voltage source to the second control node while the conductive line is selected; conductive line charging control circuitry connecting the high voltage source to the conductive line and responsive to the second control node, for selectively transferring charge from the high voltage source to the conductive line while the conductive line is selected; and conductive line isolation circuitr

Abstract: An EEPROM segment bit line page memory array includes a plurality of bit lines extending in a Y-direction; a plurality of word lines extending in an X-direction; a plurality of sub-bit lines extending in the Y-direction; a plurality of segment select word lines extending in the X-direction; a plurality of segment select devices arranged in a segment select row; and a plurality of EEPROM floating gate memory devices arranged in the X- and Y-directions. Each of the segment select devices connects one of the sub-bit lines to a corresponding one of the bit-lines. Plural gates of the segment select devices in each segment select row are connected to one of the segment select word lines. Each of the memory devices connects adjacent sub-bit lines, and corresponding control gates of plural memory devices in a memory device row arc electrically connected to one of the word lines.

Abstract: An EEPROM floating gate memory device includes: a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 Å to 1000 Å of gate oxide; an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 15 Å to 150 Å of tunnel dielectric; and a control gate disposed over and insulated from the floating gate and the channel between the floating gate and the buried source. Both the floating gate and the channel underneath are self-aligned to and flanked by the field oxide in the trench along the direction perpendicular to the channel current flow. The add-on floating gate forms both a self-aligned endcap on the field oxide and the self-aligned tunnel area on the buried drain. The architecture allows a reduction in memory cell size.

Abstract: A self-decoding charge pump for charging word lines or bit lines of a semiconductor memory array such as an EEPROM includes a passive, parallel-plate ONO capacitor for coupling voltage pulses generated by an oscillator to a charge transfer node. The voltage pulses received at the charge transfer node control the transfer of increments of charge from a high-voltage generator to a selected word line. Large-area capacitive coupling may be used without causing significant carrier injection into the substrate. In one configuration exploiting the floating-gate EEPROM semiconductor geometry, plural stacked capacitors are used, allowing a doubling of the capacitance per surface area relative to a single-capacitor configuration. Plural oscillators generating lower-amplitude signals can be used with one high-voltage generator.

Abstract: An EEPROM memory array divided into a plurality of sectors having R word lines with each sector containing S bit lines, for a total of R.times.S bit-line/word-line intersections. At each intersection there is a single transistor EEPROM memory cell with its drain connected to a bit line and its gate connected to a word line. The sources of all the cells in each sector are interconnected to a sector select line. The Fowler-Nordheim tunneling mechanism is used to accomplish erase and write operations to the memory cells. The embodiment also includes a data latch array having R data latch rows, each of which is dedicated to storing a group of S data bits to be serially written into cells of the memory via a particular one of the R word lines. A data input-output buffer has S data inputs for supplying groups of S data bits in sequential steps to S latches within each of the data latch rows, to form S columns of R data bits within the data latch array.