Abstract: A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area.