Abstract: A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.