Patents Assigned to UDMTEK
  • Patent number: 12346084
    Abstract: The present disclosure discloses a master pattern generation method which is a major pattern in a repeated cycle by analyzing programmable logic controller (PLC) logic, and a method for training a model that may analyze an error of a cycle using the generated master pattern. The master pattern generation method and the training method for a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and can be understood by humans.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: July 1, 2025
    Assignee: UDMTEK
    Inventors: Gi Nam Wang, Jun Pyo Park, Yeon Dong Kim, Nam Ki Kim, Hee Chan Yang, Yoon Woo Ha, Seung Jong Jin
  • Publication number: 20240168450
    Abstract: The present disclosure discloses a method of generating a master state that is a normal state in a repeated cycle by analyzing log data output from a programmable logic controller (PLC). In addition, a method of generating log data as graph data as data preprocessing for generating a master state is disclosed. The method of generating a master pattern and the method of training a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and can be understood by humans.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 23, 2024
    Applicant: UDMTEK
    Inventors: Gi Nam Wang, Jun Pyo Park, Seung Woo Han, Kang Hee Han, Min Young Jung, Sang Chul Yoo, Geun Ho Yu
  • Publication number: 20220342375
    Abstract: The present disclosure discloses a master pattern generation method which is a major pattern in a repeated cycle by analyzing programmable logic controller (PLC) logic, and a method for training a model that may analyze an error of a cycle using the generated master pattern. The master pattern generation method and the training method for a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and cats be understood by humans.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 27, 2022
    Applicant: UDMTEK
    Inventors: Gi Nam Wang, Jun Pyo Park, Yeon Dong Kim, Nam Ki Kim, Hee Chan Yang, Yoon Woo Ha, Seung Jong Jin