Patents Assigned to ULTRAMEMORY INC.
  • Patent number: 11183484
    Abstract: The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 23, 2021
    Assignee: ULTRAMEMORY INC.
    Inventors: Fumitake Okutsu, Takao Adachi
  • Patent number: 11094367
    Abstract: Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 17, 2021
    Assignee: ULTRAMEMORY INC.
    Inventor: Yasutoshi Yamada
  • Patent number: 10937765
    Abstract: A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 2, 2021
    Assignee: ULTRAMEMORY INC.
    Inventors: Naoki Ogawa, Toshitugu Ueda, Kazuo Yamaguchi
  • Patent number: 10868528
    Abstract: Provided is a signal output device capable of appropriately outputting a signal even when a received signal amount is low. A signal output device is provided with: a high-side comparator; a low-side comparator; a high-side AC coupling unit which is connected to one end of the input terminal of the high-side comparator, and removes a DC component from either a high signal or a low signal; a low-side AC coupling unit which is connected to one end of the input terminal of the low-side comparator, and removes a DC component from either a high signal or a low signal; and a threshold output unit which outputs high-side threshold DC voltage to be combined with the output of the high-side AC coupling unit, and also outputs low-side threshold DC voltage to be combined with the output of the low-side AC coupling unit.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 15, 2020
    Assignee: ULTRAMEMORY INC.
    Inventor: Naoki Ogawa
  • Patent number: 10861530
    Abstract: The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Ultramemory Inc.
    Inventors: Yasutoshi Yamada, Ryuji Takishita
  • Patent number: 10741525
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 11, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Ryuji Takishita, Takao Adachi
  • Patent number: 10714151
    Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 14, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Patent number: 10615850
    Abstract: The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 7, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yuji Motoyama, Takao Adachi
  • Patent number: 10529385
    Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 7, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Patent number: 10483242
    Abstract: A semiconductor device of the present invention is provided with a plurality of memory chips laminated to each other, each of said memory chips having: a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 19, 2019
    Assignee: ULTRAMEMORY INC.
    Inventors: Naoki Ogawa, Toshitugu Ueda, Kazuo Yamaguchi
  • Patent number: 10269734
    Abstract: A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 23, 2019
    Assignee: ULTRAMEMORY INC.
    Inventors: Motoaki Saito, Takao Adachi
  • Publication number: 20190043537
    Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
    Type: Application
    Filed: December 22, 2016
    Publication date: February 7, 2019
    Applicant: ULTRAMEMORY INC.
    Inventors: Yasutoshi YAMADA, Kouji UEMURA, Takao ADACHI