Patents Assigned to UltraSource, Inc.
  • Patent number: 8362368
    Abstract: The system contains a substrate having at least one electrical trace formed thereon. An opening is formed in the substrate. The opening comprising at least one wall. An electrically conductive fill is formed in the opening. The electrically conductive fill is chemically bonded to the wall and electrically contacted with the electrical trace.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 29, 2013
    Assignee: Ultrasource, Inc.
    Inventors: Michael Casper, Craig Hare, Adam Cook
  • Patent number: 7446388
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 4, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 7425877
    Abstract: A system and method for the fabrication of high reliability high performance Lange couplers (optionally including capacitors (1011), inductors (1012), multi-layer interconnects (1013), and resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed Lange coupler method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: March 26, 2005
    Date of Patent: September 16, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 7327582
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 5, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz