Abstract: A radio frequency (RF) receiver has an antenna, a low-noise amplifier, a sigma-delta frequency synthesizer/voltage-controlled oscillator (VCO), an in-phase and quadrature (I/Q) mixer, a channel filter, and a digital baseband circuit. The digital baseband circuit has a demodulator, a preamble detection and carrier frequency offset (CFO) estimation circuit, and a CFO to sigma-delta modulation (SDM) input mapper. A preamble field of a digital demodulated signal generated by the demodulator is detected by the preamble detection and CFO estimation circuit. The RF receiver simultaneously compensates its CFO and optimizes a bandwidth of the channel filter based on the detection of the preamble field of the digital demodulated signal by the preamble detection and CFO estimation circuit.

Abstract: A signal receiver includes a multiplexer, a sub-sample analog-to-digital converter (ADC) and a received signal strength indicator (RSSI) estimator for a signal receiver with multiple stage cascade amplifiers architecture. The multiplexer may select one of the input signal of each stage of cascade amplifiers or the last stage output signal of cascade amplifiers as a selected signal according to a selection signal. The sub-sample ADC may perform a sub-sampling operation using the selected signal to generate sampled data. The RSSI estimator may calculate a RSSI value corresponding to the selected signal according to the sampled data.

Abstract: A remote controller comprises a wireless communication interface and a processing unit. The wireless communication interface is communicatively connected with another remote controller. The processing unit is electrically connected with the wireless communication interface. The processing unit generates a first identification code and a second identification code and transmits the first identification code and the second identification code to the another remote controller through the wireless communication interface. The another remote controller transmits the first identification code and the second identification code to a controlled device to establish an indirect pairing relationship between the remote controller and the controlled device and a direct pairing relationship between the another remote controller and the controlled device. A pairing method of remote controllers is also disclosed.

Abstract: A two path direct frequency modulation system is disclosed. The system includes a Varactor, a voltage-controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors, and a frequency deviation capacitor bank including a second plurality of switchable capacitors. The method includes switching on or off a number of the first plurality of switchable capacitors to obtain a desired frequency band and determining number of cycles within a first predetermined time to obtain a first count, switching on or off a number of the first plurality of switchable capacitors or of the second plurality of switchable capacitors to change the desired frequency band and determining number of cycles within a second predetermined time to obtain a second count, and modulating a data signal by switching on or off a switchable capacitors of the second plurality of switchable capacitors according to the first and the second count.

Abstract: A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.

Abstract: A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.

Abstract: An IEEE 802.15.4 DSSS Offset-QPSK device is proposed that allows an existing system to transfer Offset-QPSK modulation signal into MSK modulation signal, then deliver the MSK modulation signal without DSSS to increase payload data transmission rate. On-the-fly detection of whether a low data rate or a high data rate encoding mode is used for a received frame is attained by the transmitter setting a predetermined bit in the frame length byte of a transmitting frame. Thus an extra high data rate transmission for IEEE 802.15.4 DSSS Offset-QPSK systems can be provided.

Abstract: A circuit for RSSI estimation includes a cascaded chain of variable gain amplifier stages, a threshold detector configured to output an indication signal according to a comparison of output of the cascaded chain of variable gain amplifier stages with a predetermined threshold, and an automatic gain controller configured to adjust gain of at least one variable gain amplifier of the cascaded chain of variable gain amplifier stages according to the indication signal. Each stage may include a switch module configured to electrically connect or disconnect an input of the variable gain amplifier of the at least one variable gain amplifier stage to/from an output of a previous variable gain amplifier stage according to a switch control signal.

Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.

Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.

Abstract: A multi-stage frequency offset (FO) estimation and compensation method and its circuit are described. The method includes performing at least a stage of primary-level FO estimation and compensation procedure, and a stage of advance-level FO estimation and compensation procedure. The first stage receives an input carrier signal of a larger FO and outputs a corrected carrier signal with an estimation error within the required estimation range of the next stage, to the next stage. Generated and fed forward stage-by-stage, the corrected carrier signal free of FO may be approached. Besides, since a feed-forward rather than a closed-loop approach is employed, the SNR requirement may be lower. Also, at primary-level, modulation may be first removed so the whole input carrier signal may be used to estimate FO; at advance-level, the periodic PN sequence in the input carrier signal may be utilized to estimate FO, thereby no dedicated training symbols are required.

Abstract: Apparatus for positioning and method for the same are disclosed. The apparatus comprises two transceivers and four time-to-digital converters. The time-to-digital converters compare the phase difference between two signals, one is the crystal oscillation and the other is the phase of the IF (intermediate frequency) signal extracted before ADC receiving by the transceiver. The method comprises the following steps: The first place transmits a first wireless signal by a first transceiver to the second place. The second place then responds a second wireless signal by a second transceiver to the first place. The first phase difference at the first place is then measured by the time-to-digital converter. The second phase difference at the second place is also measured. The distance between the first place and the second place is proportional to one half of the sum of first phase difference and the second phase difference.

Abstract: A wireless network system for data transmitting securely is disclosed. The system comprises a central control end for generating a cipher password per predetermined time unit. The central control end has a first Zigbee chip, a computer terminal for a user to input parameters, and a cryptographic algorithm program provided wherein the cryptographic algorithm program and the parameters are provided for password encryption using the cryptographic algorithm program is run by a microprocessor of the first Zigbee chip. The system also comprises a data transmitting end and a several data receiving ends. The data transmitting end using the Zigbee decrypts the cipher password and encrypts the data file using the plain password and the Zigbee chip. The data receiving ends using the Zigbee decrypt the cipher password and decrypt the cipher data file into plain data file by the WiFi chips using plain password.

Abstract: A CMOS cross-coupled differential voltage controlled oscillator is provided with a pair of oscillator outputs. The oscillator includes a current control unit, a first cross-coupled differential pair, an inductor unit, a capacitor unit, a second cross-coupled differential pair and a voltage controller. The current control unit is coupled between a relatively-high voltage and a relatively-low voltage. The first cross-coupled differential pair, the inductor unit, the capacitor unit and the second cross-coupled differential pair are coupled between the pair of oscillator outputs. According to the present invention, the inductor unit is provided with a midway node. The voltage controller is coupled and powered by the midway node.

Abstract: A spread spectrum receiver whose de-spreading process based on transformed spreading codes is provided. Instead of de-spreading with original spreading codes, this approach de-spreads received signal with the spreading codes transformed from the original codes in order to eliminate the negative impact of system impairments such as frequency offset to a spread spectrum receiver. Before de-spreading with the transformed code, the received signal goes through the same transformation as the original codes do. After a transformation, the transformed codes may exist some undesirable property such as spreading code having DC content. An approach is given to cancel unwanted side effects relating the transformed spreading codes. The approaches are very effective for spread spectrum system based on frequency modulation scheme such as MSK.

Abstract: A method and an apparatus for bit-rate enhancement and a wireless communication system using the same are disclosed. According to the present invention, two approaches are provided for bit-rate enhancement: one is an increase of chip-rate and the other is a decrease of chip number associated with on symbol. As such, the transmission bit-rate can be enhanced significantly so as to facilitate the applications of wireless voice communications or security.