Abstract: In an Ultra Accelerator Link (UALink)-based network, a centralized controller receives identity information and operational state of switches and ports from management agents, assigns a unique accelerator identifier to each accelerator, generates forwarding entries based on the received information wherein each forwarding entry maps a destination accelerator identifier to an egress port, and distributes the forwarding entries to the switches via the management agents. In some implementations, the centralized controller manages virtual partitions (such as virtual pods) by generating forwarding entries that restrict traffic to a designated subset of accelerators, distributing the forwarding entries, and after installation, enabling switch ports associated with the designated subset to carry transactions. The enabling may be applied to the switch ports associated with the designated subset.

Abstract: Implementations for hierarchical error recovery with scoped containment in an accelerator interconnect network. In some implementations, a system comprises accelerators coupled to switches via protocol-level interface links, each switch comprising one or more logical switches. Upon a link failure on a first logical switch, a centralized controller removes forwarding entries on the first logical switch from a virtual partition while maintaining forwarding entries on a second logical switch, enabling continued operation at reduced bandwidth. In some implementations, the centralized controller applies different recovery strategies based on the failed component type: for link failures, removing forwarding entries on the impacted logical switch; for accelerator failures, removing forwarding entries to the failed accelerator across all logical switches; and for switch failures, re-configuring the switch and re-installing forwarding entries after restart.

Abstract: Implementations for in-network arithmetic reduction with AI-optimized datatypes and configurable precision in an accelerator interconnect switch. In some implementations, a switch for a UALink-based network comprises a circuit configured to receive a collective read request specifying a reduction operation and a datatype encoded in a source identifier field, receive data from a plurality of accelerators, perform the reduction operation according to the datatype, and return a reduced result. The source identifier field may carry a physical accelerator identifier for non-collective requests. In some implementations, the switch receives data in an input datatype, performs reduction, and converts the result to a different output datatype, with the input and output datatypes independently configurable per collective request. The circuit may convert data to an intermediate precision for computation to prevent precision loss during reduction of compressed floating-point formats.

Abstract: Implementations for collective operation resilience in a chiplet-based accelerator interconnect. In some implementations, a system for a UALink-based network comprises a chiplet die with stations coupled to an accelerator die via a die-to-die interface, switches with group tables identifying groups of accelerators for collective operations, and a centralized controller. Upon detection of a station fault on the chiplet die, the centralized controller identifies group table entries on the switches that reference accelerators coupled to the faulted station and updates the entries to exclude those accelerators, enabling collective operations to continue with reduced membership. In some implementations, an accelerator die coupled to chiplet dies redistributes transaction layer flits from a faulted chiplet die to operational chiplet dies, and the centralized controller updates forwarding entries on switches to reflect the changed connectivity.

Abstract: Implementations for compressed transaction layer encoding of collective operations in accelerator networks. An accelerator for an accelerator interconnect network may encode both collective operation requests and unicast requests into a compressed request field of a transaction layer flit using a shared multi-bit command field, enabling collective operations to achieve the same bandwidth efficiency as unicast operations at the transaction layer. The accelerator may further process compressed responses by extracting a single-bit indicator that distinguishes collective operation responses from unicast responses without reference to the original request, enabling stateless response differentiation at the receiver. The compressed encoding may overload existing identifier fields to carry group identifiers for collective operations while retaining physical accelerator identifiers for unicast operations.

Abstract: Implementations for switch-offloaded block collective operations with autonomous memory access in an accelerator interconnect. In some implementations, a switch for a UALink-based network comprises a queue for storing collective operation parameters and a circuit configured to receive an invocation request carrying a control block specifying collective parameters, issue read requests to a group of destination accelerators, perform a reduction operation on received data, issue write requests to write reduced data, and write a completion status to a status buffer in the accelerator. The switch may constrain generated addresses to a bounded memory region using an address mask register. In some implementations, the switch manages queue resources through dynamic allocation of queue partitions, concurrent processing of collective operations from different partitions, and completion of outstanding operations before releasing allocated entries upon deallocation.

Abstract: Implementations for a security manager architecture within an accelerator network switch that manages encryption keys and attestation for multi-tenant workloads. As AI accelerator pods deploy encrypted in-network collective operations across shared switch infrastructure, some implementations include a switch comprising a security manager with a key storage region isolated from other switch firmware. The key storage region stores per-partition encryption keys with cross-partition inaccessibility, and automatically zeroizes all key material for a partition upon transition to a stop state.

Abstract: Implementations for propagating data errors through encrypted interconnects without causing false authentication failures. A device in a UALink-based network detects a data error indicator on a data beat of a transaction and excludes the data beat from encryption and authentication tag computation by a port encryption engine. Bytes and byte enables of the data beat are replaced with a predetermined value, and the data beat is replaced with error indication messages in an outbound flit stream. At a receiving device, a transaction layer detects the error indication messages, asserts a data error indicator for the corresponding data beat, and a decryption engine excludes the data beat from decryption and authentication tag verification. The authentication tag verification succeeds for non-poisoned data beats despite the presence of poisoned beats. Implementations may apply to accelerators, switches, integrated circuits, active cables, and collective operations in the UALink-based network.

Abstract: In some implementations, a management system for an accelerator network comprises a plurality of devices, each comprising a protocol-level interface port and configured to advertise vendor-defined capabilities via a management interface, and a centralized controller configured to discover the vendor-defined capabilities during device admission, catalog the discovered capabilities, and configure the devices based on the cataloged capabilities. The centralized controller may identify compatible capabilities between devices coupled by a link and configure the compatible capabilities.

Abstract: Implementations for neighbor validation and topology verification in an accelerator interconnect network. In some implementations, a device for the network comprises a port with a data link layer, a transaction layer, and a protocol level interface. The data link layer exchanges device identification messages with a link partner after reaching an operational state. A circuit compares received identification information with expected information configured by a management agent, and the transaction layer is gated by the circuit - enabled when the circuit indicates a validated state, and blocked when the circuit indicates an invalid state. In some implementations, a centralized controller distributes expected neighbor identifiers to devices based on an intended physical topology, receives neighbor validation results, and verifies that the complete set of results is consistent with the intended topology before distributing forwarding entries.

Abstract: Implementations for hierarchical telemetry collection with per-layer monitoring in an accelerator interconnect network. In some implementations, a telemetry system comprises devices with protocol-level interface ports managed by management agents. A telemetry collector connects with read-only access and the management agents support at least two subscription modes: one reporting operational state changes upon occurrence, and another reporting per-port telemetry data at a configurable sampling interval. When a device cannot push telemetry, the management agent may poll the device and report the data transparently. In some implementations, each port maintains per-layer telemetry counters comprising physical layer error correction histograms, data link layer flit counters, transaction layer credit utilization histograms, and port performance byte counters. The credit utilization histograms may include bins indicating time at different utilization levels, enabling congestion detection and health assessment.

Abstract: In accelerator-to-accelerator communication, scaling training and inference workloads across large numbers of accelerators may motivate the use of multiple physical paths between communication endpoints to increase aggregate bandwidth. A device in a UALink-based network may assign each outgoing transaction a transaction tag comprising an epoch number and a sequence number, and may encrypt each transaction using authenticated encryption with an initialization vector that embeds the transaction tag in an invocation field along with a counter value. A receiver may extract the transaction tag from a received encrypted transaction, reconstruct the initialization vector using the extracted tag, and decrypt the transaction independently of arrival order.

Abstract: Implementations for virtual partition lifecycle management with collective operation resource allocation in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises switches with group tables and queues for collective operations, and a centralized controller that, upon creating a virtual partition (which may be a virtual pod), programs forwarding entries and then programs group table entries and allocates queue entries for accelerators within the virtual partition. The centralized controller may deactivate group table entries and deallocate queue entries before removing forwarding entries on teardown. In some implementations, the centralized controller maintains per-virtual-partition resource accounting of group table entries and queue entries allocated to each virtual partition, and enforces per-virtual-partition quotas by rejecting allocation requests that would exceed a configured quota.

Abstract: Implementations for verifying integrity of encryption engines in a UALink-based network. A device comprising a port encryption engine calculates a CRC value over plaintext content of a message before encryption, encrypts the CRC value using a portion of an encryption keystream that follows the portion used for message encryption, producing an encrypted CRC, and computes an authentication tag over the encrypted content and the encrypted CRC. The encrypted CRC does not increase bandwidth consumed by the message. At a receiving device, a CRC is independently recalculated from decrypted content, encrypted using a corresponding keystream portion, and compared via authentication tag verification. A fault in either the encryption engine or a decryption engine at the receiving device causes an authentication tag mismatch, enabling detection of internal crypto engine faults without additional protocol overhead.

Abstract: As AI accelerator pods scale to hundreds of accelerators connected through encrypted switches, some implementations for directional key derivation and targeted key management on encrypted links, include a circuit configured to derive encryption keys using a key derivation function with a context value that includes a device pair type field. The device pair type field has different values for the accelerator-to-switch direction and the switch-to-accelerator direction, producing mathematically distinct encryption keys for each direction on the same physical link. Some implementations further include a key management message format comprising a target type field indicating whether a key operation targets an accelerator or a switch. When an accelerator receives a key management message targeting a switch, the accelerator drops the message and signals an error. When a switch with collective security enabled receives a key management message targeting a switch, the switch performs the specified key operation.

Abstract: Implementations for synchronizing state between a centralized controller and a management agent in an Ultra Accelerator Link (UALink)-based network. The centralized controller and the management agent synchronize state through a plurality of ordered phases over a connection. The ordered phases comprise negotiating communication parameters, the management agent transmitting identity information of switches and ports, the centralized controller transmitting intended configuration, the management agent transmitting current operational state, and the centralized controller transmitting forwarding entries for installation on the switches. In some implementations, the connection comprises a bidirectional streaming connection carrying messages with phase identifiers indicating a current protocol phase. The ordered phases may be executed in sequential order, and a connection may be closed upon receiving a message with a phase identifier inconsistent with the current protocol phase.

Abstract: In some implementations, a switch for an accelerator network comprises a circuit configured to perform reduction operations comprising vendor-defined reduction operations, wherein the switch advertises the vendor-defined reduction operations via a management interface, each identified by an operation encoding within a reserved range, and receives and executes collective requests specifying vendor-defined reduction operations using a group identifier for routing to a group of accelerators. In some implementations, a system comprises a switch with a circuit configured to process vendor-defined collective types, each identified by a type encoding within a reserved range, wherein the switch provides vendor-defined collective type descriptors defining collective behavior of the vendor-defined collective types, and a centralized controller configured to program the switch based on the descriptors.

Abstract: Implementations for multi-switch group table consistency management for in-network collective operations in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises a plurality of switches with group tables and a centralized controller that computes group table entries for collective groups spanning multiple switches, programs the entries on each switch, and verifies consistency across the switches. The centralized controller may use a three-phase activation protocol, programming entries with valid indicators cleared, verifying consistency, and then activating. In some implementations, the centralized controller maintains a topology model of the network, detects topology changes such as link or accelerator failures, identifies group table entries affected by the change, and updates the affected entries on each switch to maintain consistency between group membership and network reachability.

Abstract: Implementations for chiplet fault management through hierarchical error reporting and coordinated recovery in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises a chiplet die coupled to an accelerator die, a management agent on the accelerator die, and a centralized controller. Upon fault detection, the chiplet die transmits a fault notification to the accelerator die, the management agent reports the fault to the centralized controller, and the centralized controller determines a recovery action based on the fault identifier and severity. In some implementations, the accelerator die reports the fault through dual paths, to a host processor via CXL or PCIe error reporting and to the centralized controller via the management agent, and the host processor and the centralized controller coordinate recovery, with the host managing workload-level recovery and the centralized controller managing network-level recovery.

Abstract: Implementations for management resilience with route persistence and state reconciliation in an accelerator interconnect network. In some implementations, a system comprises accelerators coupled to switches via protocol-level interface links, the switches storing forwarding entries in hardware, each forwarding entry mapping a destination accelerator identifier to an egress port. A centralized controller generates and distributes the forwarding entries via management agents. The forwarding entries persist in the switches independently of the centralized controller, and when the controller fails, the switches continue routing transactions and executing workloads continue. In some implementations, upon recovery, the centralized controller re-establishes connections to management agents, re-gathers identity, configuration, and operational state, identifies discrepancies between intended and actual configuration, pushes corrections, and recalculates forwarding entries.