Abstract: A process forms electrical interconnects between memory bits in a magnetoresistive memory device. An initial dielectric layer is formed to overlie a semiconductor substrate. A magnetoresistive storage layer is formed over the initial dielectric layer. An electrically conductive stop layer that is selective to etch processes and is mechanically hard is deposited over the magnetoresistive storage layer. A hardmask layer is formed to overlie the stop layer. The hardmask layer is etched to expose the stop layer. The stop layer and the magnetoresistive storage layer are etched using ion milling until the initial dielectric layer is exposed, defining individual magnetoresistive memory bits. An isolation layer is formed over the hardmask layer and in the etch regions between magnetoresistive bits. The isolation layer is planarized using chemical mechanical polish (CMP) until the stop layer is exposed.