Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).

Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces.

Abstract: Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).

Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits.

Abstract: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

Abstract: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

Abstract: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

Abstract: Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL, SSTL, LVDS, MIPI, or MDDI interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present invention provide excellent solutions to support high performance interface while consuming much lower power.

Abstract: Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL or SSTL interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present invention provide excellent solutions to support high performance interface while consuming much lower power.

Abstract: High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.

Abstract: Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.

Abstract: A semiconductor memory array comprises a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.

Abstract: This invention discloses a dynamic random access memory (DRAM) memory cell. The DRAM memory cell includes a first transistor-capacitor circuit connected to a first bitline BL and a second transistor-capacitor circuit connected to a second bitline BL#. The memory cell further includes a gate of the first transistor connected to a gate of the second transistor. The DRAM cell further includes a sense amplifier connected to the first bit line BL and the second bit line BL# for measuring a binary bit from sensing a voltage difference between the first and second transistor-capacitor circuits independent from a pre-charged bit-line voltage.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction. The EPROM memory device further includes a plurality of word lines intersected with the first-direction first-level bit lines. The EPROM memory cell array further includes a plurality of EPROM memory cells wherein each of the plurality of memory cells being coupled between one of the first-direction first level bit lines and one of the word lines for storing data therein. And, the EPROM memory device further includes a plurality of different-direction first level bit-lines disposed along at least one different direction different from the first direction.

Abstract: A semiconductor memory array comprises a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.

Abstract: A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second wordlines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.