Abstract: An electrical circuit provides a fixed frequency switching regulator, having improved dynamic response, and a low count of external discrete elements. The circuit can be used at 100% duty cycle and does not require a minimum load or the components usually found in such circuits for compensation. A current source is used to charge a timing capacitor. A comparator is used in conjunction with a hysteresis circuit so that as the timing capacitor is charged the voltage on one input of the comparator rises until reaching a set input voltage level whereupon the timing capacitor is discharged to ground. A PWM latch logic element is used to control output to a control switch, a FET, so that positive going output pulses are received at an output terminal. A divider network between the output terminal and the timing capacitor along with a switch controlled by the PWM latch element are used for slope compensation for maintaining operational synchronization to the oscillator.