Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method is disclosed for manufacturing a discrete package for housing at least one integrated circuit die with electromagnetic interference shielding. The method may utilize a lead frame with a central die paddle and outwardly extending leads. The die paddle may have a top surface and an opposing bottom surface. The method may also have at least one integrated circuit die with a top surface and an opposing bottom surface. The integrated circuit die may be attached to the top surface of the die paddle. At least one conductive material bond may be established between the lead frame and the integrated circuit die. A dielectric material over mold may encapsulate the integrated circuit die and lead frame. A second dielectric material over mold may encapsulate the integrated circuit die and the lead frame. Further, a conductive coating may encapsulate the top and side surfaces of the package.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, grinding a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method of producing wettable fillets in electronic packages. A matrix of unsingulated lead frames is provided, each including a plurality of lead elements and a chip pad. Chips are attached to the chip pads and terminals on the chips are electrically connected to lead portions of the lead elements. The top portion of the package is encapsulated. Masking is applied to the bottom surface of the lead elements and the chip pads, but at least one of the lead elements has a portion of its surfaced remaining exposed. The exposed lead element surface is etched to create a fillet. The fillets, lead elements and bottom surface of the chip pads are plated, and the packages then singulated, producing packages with wettable flanks.

Abstract: A MEMS device for use in some embodiments in a microphone or pressure sensor and method of making the same wherein a portion of the package surrounding the acoustic port is deformed either away from, towards, or both away from and towards the interior of the package. By providing this raised area proximate the acoustic port, external debris is less likely to enter the acoustic port and damage the fragile MEMS die. Further, internal attachment material holding the MEMS die to the inside of the package is prevented by flowing into and obscuring the acoustic port. The advantages of this design include longer operation lifetimes for the MEMS device, greater design freedom, and increases in production yield.

Abstract: A method of producing wettable fillets in electronic packages. A matrix of unsingulated lead frames is provided, each including a plurality of lead elements and a chip pad. Chips are attached to the chip pads and terminals on the chips are electrically connected to lead portions of the lead elements. The top portion of the package is encapsulated. Masking is applied to the bottom surface of the lead elements and the chip pads, but at least one of the lead elements has a portion of its surfaced remaining exposed. The exposed lead element surface is etched to create a fillet. The fillets, lead elements and bottom surface of the chip pads are plated, and the packages then singulated, producing packages with wettable flanks.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded said to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded said to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.

Abstract: A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Abstract: A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

Abstract: A method for manufacturing a semiconductor device package to provide RF shielding. The device is mounted on a laminated substrate having conducting pads on its top surface. A molding compound covers the substrate top surface and encapsulates the devices. The substrate is disposed on a tape; the molding compound and the substrate are cut through, forming package units separated by the saw cut width and exposing a portion of a conducting pad. In an embodiment, the tape is stretched to widen the gap between package units. A conductive shield is applied to cover each package unit and to make electrical contact with the exposed conducting pad portion, thereby connecting to a ground trace beneath the device and providing RF shielding for the device. A single-unit molding process may be used, in which the conducting pad is exposed during and after molding.

Abstract: A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract: A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality of electrical contacts (24) being exposed on opposing sides of the package (10). Features (30) are formed into electrically inactive portions of the integrated circuit die (12) to seal moisture paths and relieve packaging stress. The features (30) are formed by forming a trough (54) partially through the backside (56) of the wafer (40) in alignment with a saw street (48), the trough (54) having a first width; and forming a channel (62) extending from the trough (54) to the electrically active face (42) to thereby singulate the integrated circuit device member, the channel (62) having a second width that is less than the first width.