Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on are fresh rate control signal. Thus, the display device provides improved visibility.

Abstract: A device and method with data preprocessing are disclosed. The device with preprocessing includes a first memory configured to store raw data, and a field programmable gate array (FPGA) in which reconfigurable augmentation modules are programmed, where the FPGA includes a decoder configured to decode the raw data, a second memory configured to store the decoded raw data, and a processor, where the processor is configured to determine target augmentation modules, from among the reconfigurable augmentation modules, based on a data preprocessing pipeline, perform the data preprocessing pipeline using the determined target augmentation modules to generate augmented data, including an augmentation of at least a portion of the decoded raw data stored in the second memory using an idle augmentation module, from among the target augmentation modules, and implement provision of the augmented data to a graphics processing unit (GPU) or Neural Processing Unit (NPU).

Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

Abstract: Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: Provided is a microfluidic film including a base film, a microchannel, which is formed on the base film and through which a fluid flows, and a through passage, which is configured to pass through the base film and through which the base film stacked on an upper portion or a lower portion of the base film and the fluid communicate with each other.

Abstract: A power control method and device for minimizing frequency variation of a full-bridge induction heating inverter are provided. The power control method includes, as a switching frequency for operating the full-bridge induction heating inverter increases, defining a section of output power that is output from the full-bridge induction heating inverter to include at least a mid-power section and a low-power section and in the mid-power section and the low-power section, limiting a variation range of the switching frequency by controlling power of a switch in the full-bridge induction heating inverter using phase shift modulation (PSM).

Abstract: An all-solid-state battery has opposing first and second side surfaces and includes: a first unit cell including a first positive electrode active material layer including a first margin layer in one side direction close to the first side surface, a second negative electrode active material layer including a second margin layer in the one side direction and the other side direction, and a solid electrolyte layer disposed between the active material layers; and a second unit cell including a second positive electrode active material layer including a second margin layer in the one side direction and the other side direction, a first negative electrode active material layer including a first margin layer in the other side direction close to the second side surface, and a solid electrolyte layer disposed between the active material layers. The first unit cell and the second unit cell are connected in series.

Abstract: Disclosed is a device for lightening an artificial intelligence-based generative model including a memory that stores data for lightening the artificial intelligence-based generative model and a processor that perform operations related to lighten the generative model. The processor assigns a randomly initialized score(s) to each of weights for a dense network based on an edge-popup algorithm, finds a random subnetwork, sorts the assigned scores in each forward path, and updates the scores using backpropagation, while leaving a weight with a preset top k % score.

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

Abstract: Disclosed herein is a method of fabricating hexagonal boron nitride in which hexagonal boron nitride is epitaxially grown. A method of fabricating hexagonal boron nitride includes placing a catalytic metal in a chamber, the catalytic metal having a hexagonal crystal structure and having a lattice mismatch of 15% or less with hexagonal boron nitride (h-BN) in a chamber; and growing hexagonal boron nitride on the catalytic metal at a temperature of 800° C. or lower while supplying a nitrogen source and a boron source into the chamber.

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Abstract: The present invention relates to a room-temperature multiferroicity material, a method for preparing same, and an electronic device comprising same. According to an example embodiment of the present invention, a room-temperature multiferroicity material according to an aspect of the present disclosure comprises a compound in chemical Formula (2) below in a compound matrix in chemical formula (1) below. Chemical formula (1) (Pb1-xTMx)Fe1/2Nb1/2O3 (in chemical formula (1), TM comprises at least one selected from the group consisting of Fe, Ni and Co, and x is a number greater than 0 and smaller than 1). Chemical formula (2) ABO3 (in chemical formula (2), A comprises at least one selected from the group consisting of Pb, Bi and Ba, and B comprises Ti and/or Zr).

Abstract: This application relates to an active compensating device. In one aspect, the active compensating device includes two or more high current paths through which a second current supplied by a second device is transmitted to a first device, and a sensing unit sensing the first current on the high current paths and generating an output signal corresponding to the first current. The device may also include an amplifying unit amplifying the output signal of the sensing unit to generate an amplified current and a compensating unit generating a compensation current based on the amplified current and allowing the compensation current to flow to each of the two or more high current paths. The device may further include a first anti-disturbance unit connected in parallel to output terminals of the sensing unit, and a second anti-disturbance unit connected in parallel to input terminals of the compensating unit.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: An amorphous silicon-carbon composite, a method for preparing the amorphous silicon-carbon composite using a pyrolysis method, a negative electrode for a lithium secondary battery, and a lithium secondary battery including the same.