Abstract: Disclosed are an implantable sensor driven by an alignment key, an implantable device comprising the implantable sensor, and a biometric data measurement system comprising the implantable device. The implantable device according to the present embodiment may comprise an implantable sensor forming a magnetic dipole moment in one direction from the inside to the outside of the body, and may be inserted into the body to measure biometric data by means of the implantable sensor.

Abstract: A processor-implemented method includes determining a first quantization value by performing log quantization on a parameter from one of input activation values and weight values in a layer of a neural network, comparing a threshold value with an error between a first dequantization value obtained by dequantization of the first quantization value and the parameter, determining a second quantization value by performing log quantization on the error in response to the error being greater than the threshold value as a result of the comparing; and quantizing the parameter to a value in which the first quantization value and the second quantization value are grouped.

Abstract: An apparatus includes: a random-access memory (RAM) configured to generate an analog output signal based on an input and a weight of a neural network, the RAM including a crossbar array structure; an analog-to-digital converter (ADC) circuit configured to generate a digital output signal based on a reference signal and the analog output signal of the RAM; a first ADC scaler configured to scale the reference signal of the ADC circuit; and a second ADC scaler configured to scale the digital output signal generated by the ADC circuit.

Abstract: The present invention relates to a three-dimensional structure electrode, a method for manufacturing same, and an electrochemical element including the electrode. The present invention is characterized by comprising: (a) an upper conductive layer and a lower conductive layer which have a structure constituting an assembly within which a conductive material and a porous nonwoven fabric including a plurality of polymeric fibers are three-dimensionally connected in an irregular and continuous manner, thereby forming a mutually connected porous structure; and (b) an active material layer forming the same assembly structure as the conductive layers and forming a three-dimensionally filled structure in which electrode active material particles are uniformly filled inside the mutually connected porous structure formed in the assembly structure, wherein the active material layer is formed between the upper conductive layer and the lower conductive layer.

Abstract: A biometric information measurement system and method are disclosed. A biometric information measurement system according to an embodiment of the present invention may comprise an implant device that is inserted into the human body so as to measure biometric information and an external device that transmits a signal to the implantable device while sweeping a frequency.

Abstract: Disclosed are an electrode for gas generation, a method of preparing the electrode, and a device including the electrode for gas generation. The electrode includes a gas generating electrode layer and a three-dimensional (3D) super-aerophobic layer formed on at least one portion of the gas generating electrode layer and including porous hydrogel.

Abstract: A tunnel field effect transistor includes a source region and a drain region, positioned on a substrate, a channel region positioned between the source region and the drain region and having a first length in a first direction, a gate electrode positioned on the channel region, and a gate insulating layer positioned between the channel region and the gate electrode, wherein the source region is doped with impurities of a first conductivity type and the drain region is doped with impurities of a second conductivity type that is different from the first conductivity type, and one of the source region and the drain region includes an extension region extending toward the other region, the extension region being positioned under the channel region to form a constant current independent of a gate voltage of the gate electrode.

Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Abstract: Disclosed is a TCAM device based on a ternary memory cell. A TCAM cell includes a ternary memory cell for storing ternary data and a comparison circuit for obtaining a stored value stored in the ternary memory cell and a search value input via a search line of a search driver, identifying a data match between the stored value and the search value, and outputting a result of the identification via a match line. The comparison circuit includes a first transistor pair that receives an inverted stored value that is an inverted value of the stored value of the ternary memory cell and the search value and a second transistor pair that receives the stored value of the ternary memory cell and an inverted search value that is an inverted value of the search value. The first transistor pair and the second transistor pair are connected in parallel to each other.

Abstract: A field-effect transistor for terahertz wave detection using a gate as an antenna includes a silicon substrate including a source and a drain formed outside a channel region surrounding the source, and a gate formed to be spaced apart from the silicon substrate and correspond to the channel region, on a dielectric layer formed on a surface of the silicon substrate, in which the drain has a width determined based on a first performance parameter associated with a terahertz wave reception rate of the field-effect transistor and the channel region has a width determined based on a second performance parameter associated with detection of a terahertz wave to be received by the field-effect transistor.

Abstract: Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

Abstract: A processor-implemented method includes determining a first quantization value by performing log quantization on a parameter from one of input activation values and weight values in a layer of a neural network, comparing a threshold value with an error between a first dequantization value obtained by dequantization of the first quantization value and the parameter, determining a second quantization value by performing log quantization on the error in response to the error being greater than the threshold value as a result of the comparing; and quantizing the parameter to a value in which the first quantization value and the second quantization value are grouped.

Abstract: A device and method with data preprocessing are disclosed. The device with preprocessing includes a first memory configured to store raw data, and a field programmable gate array (FPGA) in which reconfigurable augmentation modules are programmed, where the FPGA includes a decoder configured to decode the raw data, a second memory configured to store the decoded raw data, and a processor, where the processor is configured to determine target augmentation modules, from among the reconfigurable augmentation modules, based on a data preprocessing pipeline, perform the data preprocessing pipeline using the determined target augmentation modules to generate augmented data, including an augmentation of at least a portion of the decoded raw data stored in the second memory using an idle augmentation module, from among the target augmentation modules, and implement provision of the augmented data to a graphics processing unit (GPU) or Neural Processing Unit (NPU).

Abstract: A display device includes a display panel in which an active area and a peripheral area are defined, and an antenna unit including a main pattern, a first sub-pattern, and an antenna line. The main pattern is disposed on the display panel in the active area, transmits and/or receives a signal, and operates at a first frequency. The first sub-pattern is disposed on the display panel in the active area, is spaced apart from the main pattern in a first direction, is capacitively coupled to the main pattern, and operates at a second frequency different from the first frequency.

Abstract: The present invention relates to an induction heating apparatus. In order to cope with various types of containers without increasing an operating frequency of an induction heating apparatus, the present invention compares a resistance value of a container with a predetermined reference resistance value, and determines an operating mode of a switching device according to a result of the comparison. According to the present invention, it is possible to use various types of containers without increasing an operating frequency of an induction heating apparatus, by adjusting a resonance frequency of a working coil according to a resistance value of a container used in the induction heating apparatus.

Abstract: The present invention relates to a micro-object extraction method using diffusiophoresis enabling collection and extraction of micro-objects by using the concentration difference of a solution including the micro-objects to be extracted, and a micro-object identification method using same, wherein the present invention has the following advantages: desired micro-objects can be easily extracted only with a simple device by using diffusiophoresis; the collection and extraction of micro-objects can be easily controlled by changing the type of solution injected into a micro-channel; and energy usage is efficient by using self-powered energy by diffusiophoresis without separate external power required for extracting micro-objects.