Patents Assigned to Unistars Corporation
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Patent number: 10651354Abstract: An optoelectronic package includes a carrier, a light emitting die, a cover, and an encapsulation material. The carrier has a carrying plane and a wiring layer on the carrying plane. The light emitting die is mounted on the carrying plane and electrically connected to the wiring layer. The cover is connected to carrier. A cavity is formed between the cover and the carrier, and the light emitting die is within the cavity. The encapsulation material formed on the carrier surrounds the cover. The encapsulation material completely covers the interface between the cover and carrier.Type: GrantFiled: June 8, 2017Date of Patent: May 12, 2020Assignee: UNISTARS CORPORATIONInventors: Shang-Yi Wu, Liang-Kuei Huang, Pao-Ya Wang
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Patent number: 10215937Abstract: An optoelectronic package includes a wiring substrate having a holding plane, an optoelectronic chip, a reflective material, an optical element and an adhesive. The optoelectronic chip is mounted on the holding plane and electrically connected to the wiring substrate. The optoelectronic chip has an upper surface, a functional region and a side surface connected to the upper surface. The reflective material is on the holding plane and surrounds the optoelectronic chip. The reflective material covers the side surface and has an inclined surface. The inclined surface surrounds the upper surface and extends from an edge of the upper surface. The height of the reflective material at the inclined surface decreases from the optoelectronic chip toward a direction away from the optoelectronic chip. The adhesive covers the reflective material and the upper surface and is connected between the optoelectronic chip and the optical element.Type: GrantFiled: April 30, 2018Date of Patent: February 26, 2019Assignee: UNISTARS CORPORATIONInventors: Shang-Yi Wu, Hsin-Hsien Hsieh
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Patent number: 10153459Abstract: An optoelectronic package includes a substrate, a light emitting chip, an optical sealant, and an optical scattering layer. The substrate has a carrying plane and a wiring layer formed on the carrying plane. The light emitting chip used for emitting a light ray is mounted on the carrying plane and electrically connected to the wiring layer. The optical sealant covers the carrying plane and wraps the light emitting chip. The optical sealant is located in the path of the light ray. The optical scattering layer covers the optical sealant. The optical sealant located in the path of the light ray is formed between the substrate and the optical scattering layer. Preferably, the refractive index of the optical sealant is larger than or equal to the refractive index of the optical scattering layer.Type: GrantFiled: July 17, 2017Date of Patent: December 11, 2018Assignee: UNISTARS CORPORATIONInventors: Shang-Yi Wu, Hsin-Hsien Hsieh
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Patent number: 10121943Abstract: A light emitting package base structure includes a carrier, a light emitting chip, a light transmission unit and a dam. The carrier has a supporting surface and an outer surface surrounding the supporting surface. The light emitting chip is disposed on the supporting surface and electrically connected to the carrier. The light transmission unit is disposed on the carrier and has a through hole. The dam is disposed between the carrier and the light transmission unit, and a hermetic receiving space is formed between the dam, the light transmission unit and the carrier. The light emitting chip is located in the hermetic receiving space and the dam has a side surface away from the hermetic receiving space. A gap is formed between the side surface and the outer surface, and the through hole is corresponded to a location between the side surface and the outer surface.Type: GrantFiled: June 11, 2017Date of Patent: November 6, 2018Assignee: UNISTARS CORPORATIONInventors: Liang-Kuei Huang, Shang-Yi Wu
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Patent number: 10062815Abstract: A light emitting device includes a carrier, a light emitting chip, and a covering part disposed on the carrier. The carrier includes a board, a guiding metal layer, and a sealing material. The board has a first surface, a second surface, and a through vent that is divided into a first partial hole and a second partial hole. The first partial hole extends from the first surface to the second partial hole, and the second partial hole extends from the second surface to the first partial hole. The guiding metal layer is formed on the second surface and in the second partial hole, and covers the sidewall of the second partial hole. The guiding metal layer extends from the second partial hole to the second surface, and does not cover the sidewall of the first partial hole and the first surface. The sealing material seals the second partial hole.Type: GrantFiled: August 9, 2017Date of Patent: August 28, 2018Assignee: UNISTARS CORPORATIONInventors: Hsin-Hsien Hsieh, Shang-Yi Wu
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Publication number: 20150226382Abstract: An electroluminescence device comprises a sandwich structure and a first luminous unit. The sandwich structure comprises a first metal layer, an insulation layer, and a second metal layer stacked in sequence along a stacking direction. The first luminous unit is disposed on a sidewall of the sandwich structure parallel to the stacking direction, wherein the first luminous unit comprises a first electrode and a second electrode connected to the first metal layer and the second metal layer by a solder ball respectively.Type: ApplicationFiled: February 11, 2014Publication date: August 13, 2015Applicant: Unistars CorporationInventors: Wen-Cheng CHIEN, Shang-Yi WU, Tien-Hao HUANG, Hsin-Hsien HSIEH
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Publication number: 20150060911Abstract: An optoelectronic semiconductor device comprises a substrate, at least one solid via plug, at least one optoelectronic semiconductor chip, a phosphor layer and a molding body. The at least one solid via plug penetrates through the substrate. The at least one optoelectronic semiconductor chip has a first electrode aligned to and electrically connected with the solid via plug. The phosphor layer covers at least one surface of the optoelectronic semiconductor chip. The molding body encapsulates the substrate, the optoelectronic semiconductor chip and the phosphor layer. The number of solid valid plugs, substrate surfaces, electrodes, bonding pad on each surface of the substrate for forming each optoelectronic semiconductor device can be, for example, two, respectively.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Applicant: Unistars CorporationInventors: Wen-Cheng CHIEN, Tien-Hao HUANG, Shang-Yi WU
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Patent number: 8866313Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.Type: GrantFiled: March 13, 2013Date of Patent: October 21, 2014Assignee: Unistars CorporationInventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
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Patent number: 8866268Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.Type: GrantFiled: July 15, 2011Date of Patent: October 21, 2014Assignee: Unistars CorporationInventors: Shang-Yi Wu, Wen-Cheng Chien, Chia-Lun Tsai, Tien-Hao Huang
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Publication number: 20140247585Abstract: A semiconductor lighting apparatus includes an illumination module and a power module. The illumination module includes a supporting member, a semiconductor light-emitting element, an electrode structure and a first connecting member. The semiconductor light-emitting element is mounted on the supporting member and electrically connected with the electrode structure. The first connecting member is mounted on a first side of the supporting member. The power module is configured to connect to the first side of the supporting member, and includes a second connecting member and a driving circuit member. The second connecting member is detachably connected with the first connecting member. The driving circuit member is electrically connected with the second connecting member and electrically connected with the electrode structure to provide a driving power to the semiconductor light-emitting element.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: UNISTARS CORPORATIONInventors: Wen-Cheng CHIEN, Shang-Yi WU, Shin-Shien SHIE
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Publication number: 20140191274Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.Type: ApplicationFiled: March 13, 2013Publication date: July 10, 2014Applicant: Unistars CorporationInventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
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Patent number: 8723214Abstract: A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency.Type: GrantFiled: June 1, 2011Date of Patent: May 13, 2014Assignee: Unistars CorporationInventors: Wen-Cheng Chien, Chia-Lun Tsai