Patents Assigned to Unisys Coporation
  • Patent number: 6170081
    Abstract: A method and system for facilitating use of a tool in heterogeneous environments and application categories in a software development framework having a storage device. First, a context object is created for storing all intermediate information generated while the tool is being used. Next, the specific environment in which the tool is going to be used is identified information about the environment is stored in the context object. The specific tasks the tool typically performs are identified and searched for any previously accomplished tasks in the framework. The results of the search are stored in the context object. Information needed for the tool to operate is retrieved from the repository and the information is supplied as input files to the tool. The tool is run with the input files and the output derived is stored as a result of running the tool. The context object is updated by analyzing the output derived from the tool.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: January 2, 2001
    Assignee: Unisys Coporation
    Inventors: James Albert Fontana, Anthony Reginald Pitchford, Christopher Eyre Smith, Mark Jeffrey Tadman
  • Patent number: 5070477
    Abstract: A port adapter for an input/output system for a large data processing system. The port adapter is coupled to an I/O processor of that system and also to main memory of the system so that when the port adapter is selected by a system interrupt message from the I/O processor, it can begin and carry on its data transmission between a selected peripheral device and main memory without further assistance. The port adapter has two peripheral interface transceivers so that it can concurrently control data transfers to at least two peripheral devices.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: December 3, 1991
    Assignee: Unisys Coporation
    Inventors: Farrukh A. Latif, Michael D. Stevens
  • Patent number: 4989172
    Abstract: Apparatus for checking and detecting erroneous start signals is provided in the arithmetic section of a high speed instruction processor and may be embodied in other types of processors. The novel logic circuits include circuits for detecting an attempted start signal while a previous instruction is still in process; logic circuits for detecting when an even arithmetic sequence and an odd arithmetic sequence other than the first sequence are being concurrently processed; and logic circuits for detecting when an AR start instruction is being attempted during a wrong minor cycle.
    Type: Grant
    Filed: February 6, 1990
    Date of Patent: January 29, 1991
    Assignee: Unisys Coporation
    Inventor: Peter B. Criswell