Abstract: Supporting limited address mode memory access involves receiving a write request from the processor targeted to a first predetermined address. A data portion of the write request includes a target address of the system memory. In response to determining the write request is targeted to the first predetermined address, the target address is sent via a system interface to be stored in a configuration register of the processor director. A memory access request targeted to a second predetermined address is received from the processor. In response to determining the memory access request is targeted to the second predetermined address, the target address is retrieved from the configuration register of the processor director. The memory access is serviced using the target address retrieved from the configuration register.

Abstract: A power-state management module in any operating environment manages power consumption of a computing device in a power-on mode. The disclosed system and method based on predetermined criteria, classify computing device activity and switch the computing device from the power-on mode to either a hibernate mode or a shut down mode. The predetermined criteria include inactive computing device time compared to a predetermined time period and operational processes present in an exemption list of processes.

Abstract: To enhance data structure processing performance, data is organized bi-directionally in a data structure. That is, depending on the value of a data key associated with an entry, the entry is stored either from a low end or from a high end of the data structure. For example, the low end of the data structure may store entries having even-valued keys, while the high end of the data structure may store entries having odd-valued keys. Subsequent data structure processing can be facilitated by searching the data structure in either a forward direction starting with the low end or a reverse direction starting with the high end, depending on whether a search key is even or odd.

Abstract: A scenario simulator processor receives a declarative file and invokes one or more data simulators to create one or more datastreams from a data structure may be built as specified by the declarative file. The declarative file may specify one or more scenario names, and a set of information corresponding to the one or more scenarios (one set for each scenario). Each set of scenario information includes one or more of the following pieces of information: parameters and settings for the data simulator and the number of threads to be started for each data simulator invoked.

Abstract: The KStore is a datastore made up of a forest of interconnected, highly unconventional trees of one or more levels. One KStore can be added to an existing KStore to create an updated KStore by traversing the trees of the KStores and incrementing the count fields to reflect the added counts of analogous nodes. New KStore structure is added as needed. A KStore can be subtracted from an existing KStore to create an updated KStore by traversing trees KStores and decrementing the count fields in the updated KStore to reflect the subtracted counts of analogous nodes. KStore structure is removed as needed. Portions of a KStore can be added or subtracted from another KStore by isolating the paths to be used for updating. Instead of incrementing or decrementing counts, a dataset of individual records can be recreated from the KStore.

Abstract: Embodiments of the present invention provide a virtualization infrastructure that allows multiple guest operating systems to run and communicate amongst each other within a host hardware partition. The host system is divided into distinct logical/virtual partitions and special infrastructure partitions are implemented to control resource management and to control physical I/O device drivers that are, in turn, used by operating systems in other distinct logical/virtual guest partitions. Host hardware resource management runs as a tracking application in a resource management “ultravisor” partition, while host resource management decisions are performed in a higher-level command partition based on policies maintained in a separate operations partition.

Abstract: Disclosure of approaches for processing database transactions against a database. In one approach, a first transaction is received that specifies an operation for changing state of a first record stored in a first database page. In processing the operation, the state of the record is changed, and information is stored in a companion page. The information includes a transaction identifier, data describing the specified operation, a page identifier of the first page, a before look and an after look of the first record for an update operation, and an after look of the first record for an insert operation. In response to a commit of the first transaction, a process determines whether a second transaction, that specifies a change in state for a second stored in the first page, is in-process. In response to determining that the second transaction is in process, the companion page is stored in an audit trail.

Abstract: A method and a system for converting logical aspects of a common warehouse model (CWM) to corresponding design items for a relational database by processing in a hierarchical manner the logical aspects and creating the corresponding design items. The logical aspects comprise entity-relationship (ER) libraries. The ER libraries comprise ER models. The corresponding design items comprise design libraries. The design libraries comprise design models.

Abstract: Various approaches for processing a B+ tree data structure are described. In one approach, in a first transaction a first insert operation to a first data page of a first index page in the B+ tree data structure is detected, and then it is determined whether performing the first insert operation would block a second insert operation in a second transaction concurrent with the first transaction. At least one empty second data page is created in response to determining that the second insert operation would be blocked by the first insert operation. The B+ tree data structure is updated to include the at least one second data page in the B+ tree data structure, and the updated index pages and second data page are committed to retentive storage. Thereafter, the first insert can be completed.

Abstract: A method of handing off connection requests from a file server to other receivers on a network includes receiving a connection request from a receiver, checking to see if the requested content is currently being provided by the file server to another receiver, and, if so, handing off the request to the another receiver.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: A usage metering system for determining computer resource utilization is described herein. Computer resource utilization is determined by accumulating instances of computer resource utilization based on array of counters. This enables an accurate determination of instances of when a predetermined threshold baseline of computer resource utilization is exceeded over an accumulated period of time. By using an array of counters to collect data rather than averaging values over time, a more accurate indication of computer resource utilization is determined. The usage metering system has little impact on computer system resources, because snapshots can be taken on a fairly infrequent basis, and any computer resource utilization calculations can be performed on computer platforms separated from the system being monitored.

Abstract: Typically, field names are saved separately from tables as metadata in modern databases. Databases did not traditionally get built into interlocking trees datastores that recorded the data as events. However, in cases where one may wish to do that, thus avoiding the need for saving separate metadata from the table data of the data base, a need was found to establish an identity for particular columns or fields when working with databases or sources of data that provide table data in field/record format. So, to build interlocking trees datastores from such records a mechanism to record such data was created, adding a column ID, preferably to each field within each record or sequence that is to be recorded. Putting the column ID or identifier is inserted into the record during particlization between each column variable. In preferred embodiments a delimiter was included between the column ID or field name and the field variable. Appropriate hardware and software systems were employed to implement the invention.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: A mechanism for isolating failures in a digital system is provided. In one embodiment, a fault table is defined for each unit in the system. Related faults are ordered within the table to reflect the time-order in which the faults would be activated during operation of the associated unit. When multiple related faults are reported for a given unit in the system, the fault that is first located when a linear search of the corresponding fault table is conducted is considered the source of the failure within the unit. If faults are reported for multiple units, the source of the failure for the system is identified using at least one of primary and second priority values assigned to the faults, timestamps obtained when the faults are reported, and an order in which the faults are logged.

Abstract: Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to identify unique values of the input vector and to produce the output vector from a hard-coded output vector when the input vector is identified and when the tied control store is enabled. The control logic also includes a plurality of spare control store entries including programmable logic configurable to identify values of the input vector and to produce the output vector from a programmable output vector when the input vector is identified and when the spare control store is enabled. One of the spare control store entries that is configured to identify a value of the input vector that none of the tied control store entries that are enabled by the entry-enables register are configured to identify is enabled.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: An apparatus for and method of enhancing reliability and performance within a cluster lock processing system having a relatively large number of commodity instruction processors which are managed by a highly scalable, off the shelf platform. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. The validity operation throughput of the clustered systems manager is increased by aging out validity entries for each of the process owners via a background operation. This minimizes the number of exclusive locks that must be utilized while performing a validity operation.

Abstract: A computing system having an apparatus for providing an inline data conversion processor. The inline data conversion processor includes a host processor interface, a network interface, a peripheral interface, and a packer stream address for defining a data transformation applied to a block of data as it passes between the host processor interface and the peripheral and network interfaces.

Abstract: A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch address. The branch address is then used to address a storage device such as a microcode RAM to retrieve one or more microcode instructions that control execution of the instruction opcode. Address generation is controlled by selecting a previously unused instruction opcode, then modifying the programmable bits as necessary to generate a desired branch address. By loading modified microcode instructions at the branch address, instruction execution can be modified without changing the hardware design.