Abstract: In a fuse programmable voltage generator providing an optimal internal voltage VCCINT, a counter outputs various values to a voltage down comparator to output corresponding internal voltages VCCINT until a desired voltage is obtained. Once the desired internal voltage VCCINT is determined, the counter is disabled and a fuse circuit is configured to substantially maintain the output of the desired internal voltage VCCINT.

Abstract: Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

Abstract: A high efficiency charge pump for low and wide voltage ranges. The charge pump includes main and secondary charge pumps, the secondary charge pump is employed to avoid the Vt.sub.N drop that the main charge pump exhibits. The secondary charge pump allows the main charge pump to pump to a theoretical maximum of 2 VCC, while maintaining an efficiency close to 40%.

Abstract: An output driver for a CMOS circuit minimizes latch-up. A P-channel transistor (14) has its source-drain path coupled in series with the source-drain path of one or more N-channel transistors (16, 12). An internally generated high voltage VCCP, higher than VCC, is applied to the moat, well, or region in which the P-channel transistor is formed, and is applied to the gate electrode of the N-channel transistor(s). In one embodiment (FIG. 3), the source of the P-channel transistor is connected directly to VCC whereas in another embodiment (FIGS. 1A/1B), it is coupled to the source-drain path of another N-channel transistor, the gate electrode of which is coupled to the high voltage VCCP. In such second embodiment, the drain of the second N-channel transistor is coupled to VCC, so that the P-channel transistor is in series between the two N-channel transistors.

Abstract: A method and circuit improves the timing of a static column mode device by extending the valid write time to be equal to the write time in a fast page mode device. In particular, the circuit extends the global write enable signal and maintains the address in the address latch to increase the valid write time. Also, the circuit of the present invention improves the noise margin in the static column mode device by decoupling the write enable and column address strobe signals after they are initially received to ignore any noise in those signals. A timer is used.

Abstract: A method and circuit for configuring I/O devices, such as a DRAM or other memory device, uses master-slave buffer circuits in configurable I/O devices. When arranged in a master-slave arrangement, the slave data buffer is adapted to receive both input data and the output of an associated master circuit. In one configuration, each data buffer outputs data based upon the input data. In another configuration, each slave buffer outputs the output of an associated master buffer. The circuit of the present invention is preferably employed with a configurable I/O device incorporated in a lead-on-chip (LOC) package, although could be used in any configurable I/O device.

Abstract: A substrate bias generator avoids using a free-running oscillator and thereby saves power in the standby mode. A clock enable signal from a regulator sets a latch in a self-timed clock circuit. The latch setting initiates a first group of clock signals (that are used by a pump circuit for pumping), at the end of which the latch is reset but concomitantly an input circuit to the latch is disabled from recognizing a new pump signal. Resetting the latch causes the clock circuit to generate a second group of clock signals used in the charge pump to prepare fully for the next demand for pumping. At the end of the second group of clock signals, a full cycle of clocks has been completed in a self-timed manner, and the input circuit to the latch is reenabled to recognize a subsequent pump signal.

Abstract: A negative charge pump circuit for low voltage and wide voltage range applications. The charge pump includes two single-stage p-type pumps. One of the pumps is used to charge a circuit node down to a threshold voltage .vertline.Vt.sub.p .vertline. less than a desired voltage. When used in such a way, the other pump will charge a substrate to a full -VCC.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method :for refreshing a DRAM are also disclosed.

Abstract: A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage for low power applications in an integrated circuit. The circuit includes separate standby and active circuits for pumping V.sub.CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V.sub.CCP. The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain V.sub.CCP. The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V.sub.CCP while minimizing power consumption in DRAM.

Abstract: A method and apparatus for generating two control signals (LPB and LNB) to activate local sense amplifier driver transistors is described. The rise and fall times of these signals as well as their levels keep the sense speed and peak currents as constant as possible over the specified voltage and temperature ranges. This is achieved preferably by using current sources based on resistors to control the rise/fall times and current mirrors or modeling circuits to set the voltage levels. Preferably circuitry is provided to determine when LNB and LPB reach intermediate and full voltage levels. The timing is set to spread out the current peak into three separate smaller peaks.

Abstract: A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.

Abstract: A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.

Abstract: A fast low-to-high voltage translator with immunity to latch-up. The circuit includes a voltage comparator and employs at least one transistor which is used to quickly pull up a node. If further uses another transistor which is capable of limiting the voltage at certain nodes in order to eliminate latch-up if a pumped power supply is provided to the circuit. Latch-up therefore is eliminated during power-up. Other transistors are utilized as voltage drop limiters to limit the voltage drop across other transistors during switching. This provides improved reliability by reducing substrate current and hot carriers.

Abstract: In a DRAM, a logic "1" is redefined as the minimum VCC value minus one threshold voltage. The word line is not bootstrapped. This intermediate voltage is applied via the sense amplifier to the bit lines during refresh. The intermediate value is controlled preferably by a comparator controlling a driver. Even when the power supply voltage rises, the intermediate voltage is held constant by comparison to a fixed reference voltage. Operating current is substantially reduced because less power is required to write data into the memory cells, since a controlled lower voltage is used.

Abstract: A reference voltage generator which compensates for temperature and V.sub.CC variations includes a constant current source and a MOS P-channel transistor. The constant current source provides a constant current over a wide range of V.sub.CC that corresponds to biasing a p-channel transistor in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor, which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor. Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor to maintain a stable reference voltage.

Abstract: A supply circuit providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors which operate as a load to develop a voltage at first and second nodes. The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor, and to the gate electrode of a drive transistor and a third transistor. The drive transistor selectively couples operating voltage to the hold line. After the logic circuit turns off, the offset voltage which has been stored on the capacitor controls the drive transistor to couple the target holding voltage to the holding line.