Patents Assigned to United Microelectonics Corp.
  • Patent number: 9847331
    Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 19, 2017
    Assignee: UNITED MICROELECTONICS CORP.
    Inventor: Po-Chao Tsao
  • Patent number: 7344954
    Abstract: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: March 18, 2008
    Assignee: United Microelectonics Corp.
    Inventors: Ta-Chuan Yeh, Ni-Min Chung, Kao-Su Huang, Yung-Chang Lin, Ruey-Chyr Lee, Chien-Kuo Wang
  • Patent number: 5861333
    Abstract: The present invention includes forming a first field oxide region (FOX) on a substrate. Buried N.sup.+ regions are then formed. Subsequently, a plurality of second FOX regions are formed. A tunneling window region between the second FOX regions is narrowed by the formation of the second FOX regions. Then a tunnel oxide is formed on the substrate. A first polysilicon layer is deposited on the first FOX, the second FOXs, the gate oxide, the tunnel oxide and the substrate. An etching step is used to define the floating gate. A dielectric layer is formed on the floating gate. A second polysilicon layer is then formed on the dielectric layer. The second polysilicon layer and the dielectric layer are etched. An ion implantation step is used to form source and drain of the gate.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: January 19, 1999
    Assignee: United Microelectonics Corp.
    Inventor: Kun-Chi Lin