Abstract: A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.

Abstract: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.

Abstract: A treatment method for a surface of a photoresist layer is provided. After forming a patterned photoresist layer over a wafer, a surface treatment step is performed to the photoresist layer by using at least one reaction gas comprising hydrogen bromide or hydrogen iodide to form a hardened layer over the surface of the photoresist layer. Wherein, the surface treatment step and the etching step are in-situ performed.

Abstract: An optical projection system can receive a red light beam, green light beam, and blue light beam. The optical projection system includes a color-combination prism, and the light beams respectively enter the color-combination prism from three surfaces and are combined into a mixed light beam, which exits from another surface. A projection lens set receives the mixed light beam to perform the projection. Each of the light beams further includes a liquid crystal reflection panel and a wire grid polarizer (WGP). The liquid crystal reflection panel is parallel to the corresponding surfaces of the color-combination prism. In the design, before the light beam entering the color-combination prism, they are first reflected by the WGP onto the liquid crystal reflection panel, and the liquid crystal reflection panels respectively with a polarizing state reflect the light beams, passing through the WGP and directly propagating toward the color-combination prism.

Abstract: The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of semiconductor wafer. The method of present invention is first to define a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to depose a dielectric layer, a undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a photoresist layer sequentially. Next, a plurality of gate patterns on the memory array area is defined and the protection layer is etched to the surface of the doped polysilicon layer. Then a plurality of gate patterns on the periphery circuit region is defined in and the doped polysilicon layer, the silicide layer and the undoped polysilicon layer are etched to the surface of the dielectric layer so as to form gates of each MOS transistors in the memory array area and periphery circuit region. Finally a spacer and source and drain region are formed around each gate.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: A contact hole model-based optical proximity correction method. The method includes building a contact hole model from the database obtained through a series of test patterns each having a plurality of contact holes of different line widths but identical distance of separation. Line width offsets due to proximity effect are eliminated by referring to the contact hole model.

Abstract: A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer. A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer to expose a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening.

Abstract: A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers, to densify the dielectric layers and to protect the dielectric layers from damage in the subsequent processes. The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the depositing process of the barrier layer. The openings formed within the hard mask layer are broad at the top and narrow at the bottom. so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.

Abstract: A LOCOS method uses a reagent mixed of etchant and oxidizer to simultaneously perform the step of forming the FOX layer and the step of removing a mask layer of the conventional LOCOS method. The applied temperature is about 950-1150° C. The etchant. such as a HF acid solution, is used to remove the mask layer, and the oxidizer, such as O2, is used to form the FOX layer on a silicon substrate.

Abstract: A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

Abstract: A dual port random access memory (RAM). The dual port random access memory includes four N-MOS transistors and four P-MOS transistors. Both the N-MOS and the P-MOS transistors are used as pass gates. More specifically, two N-MOS transistors are used as pass gate for a set of bit lines and two P-MOS transistors are used as a pass gate to another set of bit lines.

Abstract: Disclosed is a method of etching which makes the quantitative analysis possible and easier. In the prior art, chemical plasma etching is mainly by ion bombardment, and the tool used to observe the metal bulk is transmission electron microscopy (TEM), so it is very difficult and complicated to execute quantitative analysis. By using chemical plasma etching, the metal precipitate will be left almost all at the end of etching. Scanning electron microscopy (SEM) is used instead of TEM to perform the quantitative analysis.