Abstract: A method for fabricating a semiconductor device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer on the MTJ, forming a first inter-metal dielectric (IMD) layer on the first cap layer, forming a second cap layer on the first cap layer and the first IMD layer, forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer, and then planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.

Abstract: A static random access memory (SRAM) device includes a first fin-shaped structure and a second fin-shaped structure extending along a first direction on a substrate, a first dummy fin-shaped structure between the first fin-shaped structure and the second fin-shaped structure, a third fin-shaped structure and a fourth fin-shaped structure extending along the first direction adjacent to the second fin-shaped structure, and a second dummy fin-shaped structure between the second fin-shaped structure and the third fin-shaped structure.

Abstract: A wafer stacking structure includes device wafers. Each device wafer is designated as an Nth device wafer. N=1, 2, . . . , M, M?3. N is a positive integer that increases sequentially in Arabic numerical order starting from 1 to define a series of Nth device wafers. The Nth device wafers are stacked from bottom to top to form a wafer stacking structure. Each of the Nth device wafers includes an Nth front surface and an Nth back surface. An Nth metal interconnection is embedded within an Nth dielectric layer. The Nth metal interconnection and the Nth dielectric layer cover and contact the Nth front surface of each Nth device wafer. Edges of all the Nth device wafers are aligned to form a plane when N=1, 2, . . . , M?1, and an edge of an Mth dielectric layer of the Mth device wafer protrudes from the plane.

Abstract: invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, wherein the substrate includes a plurality of ternary content addressable memory (TCAM) cells, and wherein the layouts of at least two TCAM cells are mirror symmetrical to each other along a symmetry axis. Each TCAM cell comprises a plurality of transistors, and the substrate includes a plurality of fin structures arranged along a Y direction and a plurality of gate structures arranged along an X direction. Among the plurality of gate structures, there is a first gate structure connected to a search line SLB and a second gate structure not connected to the search line SLB, wherein the first gate structure is arranged in parallel with the second gate structure, the first gate structure does not overlap with the symmetry axis, and the second gate structure overlaps with the symmetry axis.

Abstract: The invention provides a paired capacitor comprising a substrate with a left region, a middle region, and a right region defined thereon, wherein the middle region is located between the left region and the right region; a first capacitor structure comprising a first lower electrode pattern and a first upper electrode pattern in different regions and layers along a vertical direction; and a second capacitor structure comprising a second lower electrode pattern and a second upper electrode pattern similarly arranged.

Abstract: An embedded high-voltage semiconductor device includes a substrate with a low-voltage device region and a high-voltage device region; an ILD layer located on the substrate; a first interconnection metal layer located on the ILD layer in the low-voltage device region a; a first IMD layer between the ILD layer and the first interconnection metal layer; a second interconnection metal layer located on the ILD layer in the high-voltage device region; and a second IMD layer between the ILD layer and the second interconnection metal layer. The second IMD layer is denser than the first IMD layer.

Abstract: The invention provides a semiconductor layout pattern, which comprises a first metal layer, wherein the first metal layer comprises a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the principal axis pattern, and a second metal layer is located on the first metal layer. A plurality of magnetic tunnel junction (MTJ) elements located on the second metal layer, wherein each magnetic tunnel junction element is arranged in a rhombic shape.

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

Abstract: A semiconductor structure includes a substrate and a first switch element disposed in a first device area of the substrate. The first switch element includes a channel region, a first gate dielectric layer, a first gate layer and a source/drain region. The channel region is disposed at the bottom of a recess in the first device area. The first gate dielectric layer has a first region and a second region extending into the recess, the first region has a first thickness; the second region has a second thickness, and the first thickness is smaller than the second thickness. The first gate layer is disposed above the first gate dielectric layer. The source/drain region is disposed in the substrate and adjacent to the first gate dielectric layer.

Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line directly on a first metal structure, a top electrode island disposed beside the bottom electrode line, a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island, and a cap layer covering a portion of the first metal structure and under the bottom electrode line.

Abstract: During a first phase, a bit line voltage is transmitted to a first input end of a sense amplifier and a reference voltage is transmitted to a second input end of the sense amplifier, so that the sense amplifier outputs data based on a first voltage difference between its first and second input ends for providing a first data signal. During a second phase, the reference voltage is transmitted to the first input end of the sense amplifier and the bit line voltage is transmitted to the second input end of the sense amplifier, so that the sense amplifier outputs data based on a second voltage difference between its first and second input ends for providing a second data signal. During a third phase, a sense margin detecting signal is provided based on the first data signal and the second data signal.

Abstract: A semiconductor structure includes a substrate, a top metal layer disposed on the substrate, a top dielectric layer disposed on the substrate and the top metal layer, at least one opening disposed in the top dielectric layer, and an aluminum layer conformally deposited on the top dielectric layer and in the at least one opening. When viewed from above, the at least one opening has a regular n-gon pattern (n is greater than or equal to 6), circular pattern or oval pattern.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.