Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

Abstract: A semiconductor device includes a substrate comprising a one time programmable (OTP) device region and a second region, a shallow trench isolation (STI) in the substrate disposed in both the OTP device region and the second region, and a first gate structure on the STI in the OTP device region. A top surface of the STI in the OTP device region is lower than a top surface of the STI in the second region. This cross-region height difference enables integration of OTP, I/O, and core devices on a single substrate and facilitates formation of dual step-shape profiles under the gate structure on the OTP device region for an enhanced and more concentrated electrical field.

Abstract: A bonded semiconductor structure includes a first wafer having a first through silicon via (TSV), a second wafer bonded to the first wafer, and a second TSV through the second wafer. The second TSV has a lower portion contacting and electrically connected to the first TSV and an upper portion on the lower portion. A sidewall of the lower portion, a bottom surface and a sidewall of the upper portion form a step-profile.

Abstract: A resistive random access memory (RRAM) includes an interlayer dielectric (ILD) layer on a substrate, a contact plug in the ILD layer, a bottom electrode on the contact plug, a resistor switching layer on the bottom electrode, and a top electrode (TE) on the resistor switching layer. Preferably, the TE includes more than one TE and the more than one TE includes titanium nitride (TiN).

Abstract: A semiconductor structure includes a first silicon substrate having a display region and a driving region, a circuit layer on the first silicon substrate, a plurality of light emitting elements on the display region, a plurality of active elements on the driving region and electrically connected to the circuit layer, and a second silicon substrate on the plurality of active elements. A plurality of first hybrid bonding pads in the driving region directly contact a plurality of second hybrid bonding pads under the plurality of active elements. A plurality of conductive pads located outside the driving region receive an input signal and have an electrical connection function different from that of the first hybrid bonding pads. A blank area is maintained between each of the light emitting elements and the second silicon substrate, avoiding manufacturing and electrical interference. A manufacturing method is also provided.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: A semiconductor structure including a first substrate, a first dielectric layer, a first oxygen doped carbide (ODC) bonding layer, a second substrate, a second dielectric layer, and a second ODC bonding layer is provided. The first dielectric layer is located on the first substrate. The first ODC bonding layer is located on the first dielectric layer. The second dielectric layer is located on the second substrate. The second ODC bonding layer is located on the second dielectric layer. The first ODC bonding layer and the second ODC bonding layer are bonded to each other.

Abstract: A semiconductor transistor structure includes a semiconductor substrate having an active area and a trench isolation region surrounding the active area; a first inter-layer dielectric (ILD) layer covering the semiconductor substrate; a metal gate embedded in the first ILD layer and overlying the active area and the trench isolation region, wherein the metal gate comprises a first portion disposed directly above the active area and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion; a hard mask layer disposed on the second portion; and a gate dielectric layer disposed between the first portion of the metal gate and the active area.

Abstract: The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a channel layer on a substrate, forming a first barrier layer on the channel layer, forming a p-type semiconductor layer on the first barrier layer, forming a first patterned passivation layer on the p-type semiconductor layer, and then forming a gate electrode on the first patterned passivation layer. Preferably, the gate electrode includes a first portion adjacent to one side of the first patterned passivation layer and a second portion adjacent to another side of the first patterned passivation layer.

Abstract: An LDMOS features a semiconductor substrate with adjacent first and second wells of differing doping types. The second well is isolated from a third well by a first STI, with the bottom of the first STI being in direct contact with a native region of the semiconductor substrate. A gate pattern is formed on the semiconductor substrate, vertically overlapping both the first and second wells. Additionally, a dummy pattern is positioned atop the first STI, and a source doped region is formed in the first well on one side of the gate pattern, while a drain doped region is positioned within the third well.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of firs providing a substrate comprising a magnetoresistive random access memory (MRAM) region, a PUF cell region, and a non-PUF cell region, forming a first metal interconnection on the MRAM region, forming a second metal interconnection on the PUF cell region, and forming a third metal interconnection on the non-PUF cell region. Preferably, the first metal interconnection and the second metal interconnection include patterns of different shapes and the first metal interconnection and the third metal interconnection include patterns of same shape.

Abstract: A method for forming a static random access memory includes the steps of providing a substrate having a plurality of active regions arranged parallel to each other, forming a lower dielectric layer on the substrate and a plurality of gate structures in the lower dielectric layer and crossing the active regions, forming a first patterned mask on the lower dielectric layer, the first patterned mask comprising a plurality of slot openings corresponding to the active regions, forming a second patterned mask on the first patterned mask, the second patterned mask comprising a plurality of stripe patterns corresponding to the gate structures, using the first patterned mask and the stripe patterns as an etching mask to etch the lower dielectric layer, thereby forming a plurality of lower contact openings that expose portions of the active regions, and forming lower contacts in the lower contact openings.

Abstract: A semiconductor device includes a semiconductor substrate, pad structures, a filling dielectric layer, and a compressive stress layer. The pad structures and the filling dielectric layer are disposed on the semiconductor substrate, and the filling dielectric layer includes a first portion and a second portion. The first portion is disposed between the pad structures in a horizontal direction. The second portion is disposed above the pad structures in a vertical direction. The compressive stress layer is disposed on the filling dielectric layer and the pad structures. The second portion of the filling dielectric layer includes an opening located above one of the pad structures in the vertical direction, the opening is filled with the compressive stress layer, and a thickness of the compressive stress layer is greater than a thickness of the second portion of the filling dielectric layer.

Abstract: A method for fabricating a resistive random access memory (RRAM) includes the steps of first providing a substrate having an alignment mark region and a RRAM region, forming an interlayer dielectric (ILD) layer on the substrate, forming a contact plug in the ILD layer of the RRAM region, forming a first bottom electrode (BE) layer on the RRAM region and the alignment mark region, and then removing the first BE layer and the ILD layer on the alignment mark region to form a trench.

Abstract: ABSTRACT OF DISCLOSURE A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate structure and a plurality of doped regions. The gate structure includes a gate conductive layer and a gate dielectric layer. The gate conductive layer is located over the substrate. The gate dielectric layer is located between the gate conductive layer and the substrate. The gate dielectric layer includes a body part and a first hump part. The body part is located on the flat surface of the substrate. The first hump part is located on a portion of the flat surface at a first edge of the body part. The thickness of the first hump is greater than the thickness of the body part. The plurality of doped regions are located in the substrate at two sides of the gate structure.