Patents Assigned to United Microelectronics Corp.
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10737932
    Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Jung-Hao Chang, Chang-Sheng Hsu, Weng-Yi Chen
  • Publication number: 20200251482
    Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Applicant: United Microelectronics Corp.
    Inventor: Chin-Chin Tsai
  • Patent number: 10734284
    Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10734276
    Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Fu-Shou Tsai, Wen-Chin Lin, Chun-Liang Liu
  • Patent number: 10734496
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20200243386
    Abstract: A method for fabricating semiconductor device includes providing a preliminary device layer, having a substrate on top and a through substrate via (TSV) structure in the substrate. A top portion of the TSV structure protrudes out from the substrate. A dielectric layer is disposed over the substrate to cover the substrate and the TSV structure. A coating layer is formed over the dielectric layer, wherein the coating layer fully covers over the dielectric layer with a flat surface. An anisotropic etching process is performed to the coating layer and the dielectric layer without etching selection until the TSV structure is exposed.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Applicant: United Microelectronics Corp.
    Inventors: CHU-FU LIN, Ming-Tse Lin, Chun-Hung Chen
  • Publication number: 20200243515
    Abstract: A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Applicant: United Microelectronics Corp.
    Inventor: Zhi-Biao Zhou
  • Patent number: 10722998
    Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Kun-Ju Li, Po-Cheng Huang, Chun-Liang Liu
  • Patent number: 10727234
    Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, Runshun Wang, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
  • Patent number: 10727397
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Patent number: 10727324
    Abstract: A bipolar junction transistor includes: an emitter region; a base region; and a collector region, wherein each of the emitter region, the base region, and the collector region comprises fin-shaped structures. Preferably, the emitter region, the base region, and the collector region are disposed along a first direction and the fin-shaped structures are disposed along a second direction, in which the first direction is orthogonal to the second direction.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Cho, Chen-Wei Pan
  • Publication number: 20200235063
    Abstract: Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer.
    Type: Application
    Filed: February 20, 2019
    Publication date: July 23, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Chun-Hung Chen, Ming-Tse Lin
  • Patent number: 10720440
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Publication number: 20200227354
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Patent number: 10714480
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: July 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10714607
    Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
  • Patent number: 10714452
    Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10714481
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: July 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee