Abstract: A testing method and a testing device for an electronic circuit are provided. The testing method includes the following steps. A test voltage signal is provided to a connection pad of the electronic circuit. A voltage regulating circuit of the electronic circuit is controlled to generate a reference voltage and provide the reference voltage to the connection pad. A voltage value of one of the test voltage signal and the reference voltage is adjusted, and a test current flowing through the connection pad is received. A measured voltage value of the reference voltage is determined according to a change in a current direction of the test current.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Abstract: An optical metasurface structure includes a substrate, a first metal rail structure, a second metal rail structure, a diffusion barrier layer, a high dielectric constant dielectric layer, and a liquid crystal material. The first metal rail structure and the second metal rail structure are disposed above the substrate. The diffusion barrier layer is disposed on the first metal rail structure and the second metal rail structure. The high dielectric constant dielectric layer is disposed on the diffusion barrier layer. The liquid crystal material is disposed above the substrate and at least a part of the liquid crystal material is located between the first metal rail structure and the second metal rail structure in a horizontal direction. The diffusion barrier layer has a first thickness, a portion of the high dielectric constant dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

Abstract: A PUF device includes a first transistor that has a first well with a first conductivity and a first channel region with a second conductivity, a second transistor that has a second well and a second channel region both with the first conductivity, and a reading circuit. When a gate-source voltage applied to these transistors is equal to 0, the first transistor and the second transistor are both in an off state. The reading circuit is electrically connected to the first transistor and the second transistor, and is used to read a plurality of first conduction states of the first transistors and the second transistor, and then to output a first set of numerical values.

Abstract: A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer on the substrate; an etch stop layer on the first dielectric layer; a second dielectric layer on the etch stop layer; a first conductor and a second conductor in the second dielectric layer, an air gap in the second dielectric layer and between the first conductor and the second conductor; and a low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap.

Abstract: A semiconductor process prediction method and a semiconductor process prediction apparatus considering overall features and local features are provided. The semiconductor manufacturing process prediction method includes the following steps. Several equipment sensing curves are obtained. The equipment sensing curves are filtered to reduce the co-linearity of the equipment sensing curves. A Dynamic Time Warping (DTW) procedure is performed to align the equipment sensing curves. The equipment sensing curves which are aligned are inputted into a Convolutional Neural Network (CNN) model to obtain a first prediction result considering the local features. A statistical analysis procedure is performed on the equipment sensing curves to obtain several statistical data. The statistical data are inputted into an Artificial Neural Network (ANN) model to obtain a second prediction result considering the overall features.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

Abstract: The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.

Abstract: A static random access memory (SRAM) includes a first memory cell. The first memory cell includes: a first pull-down transistor, a first pull-up transistor, a second pull-up transistor, and a second pull-down transistor arranged on a first segment of a first fin, a first segment of a second fin, a first segment of a third fin and a first segment of a fourth fin of a substrate, respectively. The first memory cell further includes a first diode and a second diode. The first diode includes a first conductive feature in contact with a top surface and multiple upper sidewalls of a first end of the first segment of the first fin. The second diode includes a second conductive feature in contact with a top surface and multiple upper sidewalls of a second end of the first segment of the fourth fin.

Abstract: A projection system is provided. The projection system includes at least one micro LED line and a scan optical system. The micro LED line is configured for emitting lights with a changing frequency of X times per second. The scan optical system is disposed at a downstream side of the at least one micro LED line. The scan optical system is configured to scan the lights emitted from the micro LED line with a scan rate of M seconds per scan and to project images formed of the lights to corresponding positions on a target projection plane. The projection system has a horizontal resolution of N lines. A total number n of the at least one micro LED line is smaller than N. Also, X=M*(N/n).

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a gate structure on the barrier layer, a gate spacer on the gate structure, and a gate contact on the gate spacer. The gate contact includes a first portion and a second portion respectively at two sides of the gate spacer and directly contacting the gate structure.

Abstract: A delay circuit includes a delay chain and a calibration circuit. The delay chain includes a plurality of delay cells coupled in series. The delay chain provides a delay amount, and delays a clock signal by the delay amount to generate a delayed clock signal. The calibration circuit is coupled to the delay chain, counts the number of pulses of the delayed clock signal during a preset time period to generate a count value, and generates calibration information according to the count value. The delay chain adjusts the delay amount by adjusting a transmission delay of at least one of the delay cells according to the calibration information.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

Abstract: A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

Abstract: An imprint method including the following steps is provided. Providing a first master mold including a first protruding pattern and a second protruding pattern. Providing a second master mold including a third protruding pattern. Performing a first imprint step on a first photoresist layer formed on a replica mold by using the first master mold. Performing a first etching step on the replica mold to form a first recessed portion and a second recessed portion. Performing a second imprint step on a second photoresist layer formed on the replica mold by using the second master mold. Performing a second etching step on the replica mold to form a third recessed portion overlapping the first recessed portion. Performing a third imprint step on a third photoresist layer formed on a substrate by using the replica mold. Performing a third etching step on the substrate to form a desired pattern.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, wherein the plurality of gate structures comprises at least one first gate structure and at least one second gate structure, at least one first metal layer located on the first gate structure, wherein the first metal layer is electrically connected with the first gate structure, and at least one second metal layer bridging the second gate structure and another one of the plurality of gate structures, wherein a top surface of the first gate structure is lower than a top surface of the second gate structure.