Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a substrate comprising a magnetoresistive random access memory (MRAM) region, a PUF cell region, and a non-PUF cell region, forming a first metal interconnection on the MRAM region, forming a second metal interconnection on the PUF cell region, and forming a third metal interconnection on the non-PUF cell region. Preferably, the first metal interconnection and the second metal interconnection include patterns of different shapes and the first metal interconnection and the third metal interconnection include patterns of same shape.

Abstract: The invention provides a semiconductor structure, which comprises a first silicon substrate with a display region and a driving region defined thereon, a circuit layer located on the first silicon substrate, a plurality of light emitting elements located on the display region of the first silicon substrate, a driving chip located on the driving region of the first silicon substrate and electrically connected with the circuit layer, and a second silicon substrate located on the driving chip.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

Abstract: A semiconductor device includes a bottom electrode on a substrate, a magnetic tunneling junction (MTJ) on the bottom electrode, a first cap layer on the MTJ, a second cap layer on the first cap layer, a block layer on the second cap layer, and a top electrode on the block layer. Preferably, the block layer could be made of Co-based alloy or metal nitride, in which the Co-based alloy could further include CoW alloy whereas the metal nitride could include WN.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a channel layer on a substrate, forming a first barrier layer on the channel layer, forming a p-type semiconductor layer on the first barrier layer, forming a first patterned passivation layer on the p-type semiconductor layer, and then forming a gate electrode on the first patterned passivation layer. Preferably, the gate electrode includes a first portion adjacent to one side of the first patterned passivation layer and a second portion adjacent to another side of the first patterned passivation layer.

Abstract: Provided is a flash memory including a substrate including a recess, first, second and third dielectric layers, a floating gate, source and drain regions, an erase gate, and a select gate. The first dielectric layer is disposed in the recess. The floating gate fills the recess and the first dielectric layer located between the floating gate and the substrate. The second dielectric layer covers a top surface of the floating gate away from the substrate. The source region is disposed in the substrate at one side of the floating gate. The drain region is disposed in the substrate at another of the floating gate. The erase gate is disposed on the second dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate and separated from the second dielectric layer.

Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric ((IMD) layer on a substrate and a metal interconnection in the IMD layer, forming a dielectric layer on the IMD layer, patterning the dielectric layer to form an opening, forming a bonding pad in the opening, and then forming a passivation layer on the bonding pad. Preferably, a top surface of the bonding pad includes a first curve and a sidewall of the bonding pad includes a second curve.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

Abstract: A semiconductor structure includes a semiconductor substrate; a source structure in the semiconductor substrate, wherein the source structure includes a source drift region and a heavily doped source region within the source drift region; a recessed trench disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at a bottom of the recessed trench, wherein the drain structure includes a drain drift region, a heavily doped drain region disposed within the drain drift region, and a carbon-doped surface layer on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate between the source structure and the drain structure.

Abstract: A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.

Abstract: The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

Abstract: Provided are a transistor structure and a manufacturing method thereof. The transistor structure includes a gate dielectric layer, a gate disposed on the gate dielectric layer, a spacer structure located on the gate dielectric layer and disposed on the sidewall of the gate, first, second and third doped regions, and a metal silicide layer. The first doped regions are disposed in the substrate on two sides of the gate. The second doped regions are disposed in the first doped regions, respectively. The third doped regions is disposed in the second doped regions, respectively. The metal silicide layer is disposed at the surface of the third doped regions. In the channel direction, the first doped regions extend below the gate to partially overlap with the gate, the second doped regions extends below the spacer structure, and the metal silicide layer does not extend below the gate.

Abstract: Semiconductor device and method of fabricating the same, includes a substrate, a first dielectric layer and a second dielectric layer, a bonding interface layer, and a plurality of dummy vias. The first dielectric layer and the second dielectric layer are stacked in sequence on the substrate. The bonding interface layer is disposed between the first dielectric layer and the second dielectric layer, wherein the bonding interface layer includes a first interface layer and a second interface layer stacked in sequence. The plurality of dummy vias are disposed within one of the first dielectric layer and the second dielectric layer, being located at only one side of the bonding interface layer in a vertical direction of the substrate.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a channel layer on the substrate, a first barrier layer on the channel layer, a second barrier layer on the first barrier layer, and a gate element on the second barrier layer. The first barrier layer includes a first material with a first band gap, the second barrier layer includes a second material with a second band gap, and the first band gap is greater than the second band gap.

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.