Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench and includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer, located under the trench, and connected with the first bottom electrode. The signal line structure is disposed in the trench, partly disposed on the first resistive switching element, and electrically connected with the first top electrode. The first bottom electrode includes a U-shaped structure surrounding the signal line structure, the first top electrode, and the first variable resistance layer in a horizontal direction.

Abstract: A capacitance design and a method of forming the same are provided. The capacitance design includes: a substrate, including a silicon nitride layer, a first silicon oxide layer, a silicon layer, and a second silicon oxide layer from top to bottom along a vertical direction; an opening in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer; and an insulator-shape capacitor conformally on a surface of the opening. The opening includes a trench in the silicon nitride layer, the first silicon oxide layer, the silicon layer, and the second silicon oxide layer along the vertical direction; and a first toroidal cavity and a second toroidal cavity respectively in the first silicon oxide layer and the second silicon oxide layer along a horizontal direction perpendicular to the vertical direction from the trench.

Abstract: A semiconductor process of simultaneously forming features of D-mode and E-mode GaN devices, including forming a p-GaN layer on an AlGaN layer in a first region of a substrate, sequentially forming a Al-based passivation layer and a Si-based passivation layer on the AlGaN layer and p-GaN layer, and performing a photolithography process to form gate contact openings simultaneously in the first region and a second region of the substrate, wherein the gate contact opening on first region extends through the Si-based passivation layer and Al-based passivation layer to the p-GaN layer, and the gate contact opening in second region extends through the Si-based passivation layer and Al-based passivation layer to the AlGaN layer, and the photolithography process includes an etching process and a first wet etching process, and the etching process removes the Si-based passivation layer and the first wet etching process removes the Al-based passivation layer.

Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.

Abstract: A fully-isolated metal oxide semiconductor (MOS) device includes a substrate, an isolation well, a gate structure, a source region, a gradient region, a drain region, a first well, and an electro static discharge (ESD) protection region. The isolation well is formed in the substrate, and the gate structure is formed on the isolation well. The source region and the gradient region are formed in the isolation wells on both sides of the gate structure respectively, and the drain region is formed in the gradient region. The first well is formed below the drain region in the gradient region, and the ESD protection region is formed in the first well. The isolation well and the ESD protection region have a first conductivity type, and the gradient region and the first well have a second conductivity type.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first deep well region, a second deep well region, a first well region, a second well region, a gate structure, a source doped region, and an isolation structure. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. The source doped region is located in the first well region. A part of the second deep well region is located under the source doped region. The isolation structure is disposed in the first well region. The first deep well region includes a protrusion part surrounding the second deep well region. A topmost surface of the protrusion part of the first deep well region is directly connected with a bottommost surface of the isolation structure.

Abstract: A semiconductor device includes a substrate, two first field regions, a gate structure, a first isolation structure, and a plurality of second field regions. The two first field regions are disposed in the substrate, and the gate structure is disposed on the substrate, between the two first field regions. The first isolation structure is disposed in one of the two first field regions, under one side of the gate structure. The second field regions are disposed in the substrate, wherein the second field regions are separately and sequentially arranged to surround an outer periphery of the one of the two first field regions.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first deep well region, a second deep well region, a first well region, a second well region, a gate structure, an isolation structure, and a third well region. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. The gate structure is disposed on the semiconductor substrate. The isolation structure is disposed in the first well region. The third well region is located between the isolation structure and the first deep well region in a vertical direction. A part of the first well region is sandwiched between the third well region and the second deep well region in a horizontal direction.

Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.

Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

Abstract: A method of carbon capture and recycling tetramethyl ammonium carbonate-containing solution includes providing a recycling apparatus. The recycling apparatus includes a reactor. The reactor includes a cover, a side wall and a bottom. A fluid supply tube is suspended in the reactor close to the cover. Numerous spray nozzles are connected to the fluid supply tube. Numerous nozzles are arranged on the side wall. The method of recycling tetramethyl ammonium carbonate-containing solution by using carbon dioxide is performed by using the recycling apparatus. The method incudes supplying tetramethyl ammonium carbonate-containing solution into the fluid supply tube and spraying out from the spraying nozzles. Meanwhile, the carbon dioxide-containing gas is turned on to spray the carbon dioxide-containing gas from the nozzles. The PH value of the tetramethyl ammonium carbonate-containing solution is reduced after adjusted by the carbon dioxide-containing gas.

Abstract: A semiconductor structure includes a substrate having at least one through substrate via (TSV) forming region thereon; a dielectric layer disposed on the substrate; and at least one through substrate via disposed in the TSV forming region and penetrating through the dielectric layer and into the substrate. The at least one through substrate via comprises a plurality of stress-relief slits elongating in a radial direction.

Abstract: A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.