Abstract: A method for forming vias between a multi-layer structure and an interconnect is disclosed. The method is practiced on a semiconductor substrate having a conductive region and a multi-layer structure which has a first conductive layer on top. A retardation layer is formed over the first conductive layer and a dielectric layer is formed over the entire surface of the multi-layer structure, the entire surface of the conductive region and over the surface of the substrate. A first via hole is formed through both the dielectric layer and the retardation layer to expose a portion of the first conductive layer. A second via hole is formed through the dielectric layer to expose a portion of the conductive region. A first via plug is formed in the first via hole to electrically contact the first conductive layer and a second via plug is formed in the second via hole to electrically contact the conductive region.