Abstract: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Abstract: The invention provides an apparatus and a method for rubbing the alignment layer in the LCD substrate. The rubbing apparatus of the present invention further includes a conditioning roller, in addition to the rubbing roller, to rejuvenate the rubbing roller in real time so as to lengthen the roller lifetime in the rubbing process and increase the rubbing rate. By employing the conditioning roller along with the rubbing roller, the rubbing process includes an extra conditioning step for conditioning the rubbing roller, thus shortening the production cycle time and increasing the throughput.

Abstract: An optical proximity correction method for rectifying pattern on photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

Abstract: A process for removing photoresist material without any residues left and damage to the in-process substrate is described. The present process for removing photoresist on an in-process substrate comprises the steps of providing a cover layer which is to be etched on the in-process substrate and providing a layer of photoresist material thereon. The photoresist layer is patterned, exposed and developed. Then, the developed photoresist layer is further exposed without using a mask. The cover layer is etched with the use of the patterned photoresist layer. After etching, the photoresist material is removed by a solvent.

Abstract: A low duty ratio mask has a plurality of masked layout patterns and a plurality of alternating scattering bars placed next to edges of each masked layout pattern. A phase shift of 180° exists between the alternating scattering bars and the corresponding masked layout pattern.

Abstract: A method for fabricating a flash memory is disclosed, in which a stacked gate structure comprising a floating gate and a control gate on the substrate is first formed. Ions are implanted into the substrate at one side of the stacked gate. A drain having a heavily doped region and a lightly doped region are subsequently formed. Spacers one each side of the stacked gate structure are formed. By using a photoresist layer covering the spacer at the drain end, the spacer at the source end can be reduced by an etching process. The source region of the flash memory is formed by implanting ions into the substrate using the reduced spacer as a mask.