Abstract: A microelectro-mechanical system (MEMS) device includes a substrate of a semiconductor material having thereon a movable component, a glass substrate bonded to the substrate, an electrostatic biasing layer disposed between the movable component and the glass substrate. A cavity is defined between the movable component and a top surface of the glass substrate. The electrostatic biasing layer completely overlaps with the movable component.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

Abstract: A CMOS device is disclosed, including a plurality of active regions having a length along a first direction, wherein the active regions are arranged end-to-end along the first direction and are separated by an isolation structure. A recessed region is formed in the isolation structure between the adjacent terminals of the each pair of neighboring active regions and is completely filled by an interlayer dielectric layer, wherein the interlayer dielectric layer comprises a stress.

Abstract: A CMOS image sensor integrated with 1T-SRAM is provided on a substrate having a pixel array part, a logic circuit part, and a memory part by adding only one photoresist process. There are a plurality of CMOS image sensor devices in the pixel array part, a logic circuit in the logic circuit part, and a plurality of 1T-SRAMs in the memory part, and each part is isolated by a plurality of STI regions. The 1T-SRAM includes a capacitor structure and a transistor. The capacitor structure includes a well region as a bottom capacitor plate, a capacitor dielectric layer, and a top capacitor plate formed on the substrate respectively. The transistor includes a gate dielectric layer, a gate, a drain, and a source continuous with and electrically connected to the well region.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.

Abstract: A method of fabricating a semiconductor device is disclosed. First, a substrate is provided. The substrate includes at least a transistor area having a gate structure thereon, a capacitor area having a first electrode thereon and a resistor area having a second electrode thereon. The capacitor area and the resistor area both have an isolation structure therein. Then, first spacers and source/drain regions on both sides of the gate are sequentially formed. After that, a dielectric layer and a first conductive material layer are sequentially formed on the substrate. Next, the first conductive material layer is patterned to form a third electrode in the capacitor area and a conductive layer in the resistor area. Then, second spacers are formed. Afterwards, the exposed dielectric layer is removed. Finally, a self-aligned silicide process is performed to form a metal salicide layer to cover the surface of the device.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is irradiated with UV light, and the remaining photoresist and polymer are stripped with stripping solvents after UV irradiation.

Abstract: The present invention studs oxide dielectric into trench capacitor top recesses after the formation of the trench capacitor structures. A thin (500 Å) cap buffer nitride is then deposited over the substrate. The studded dielectric and the collar oxide protect the trench capacitors during the subsequent selective dry etching, thereby forming isolation trenches having an approximately T-shaped cross section between the trench capacitors within the memory array area of the semiconductor chip.

Abstract: The present invention relates to a method which introduce a parasitic series resistance for solving electrostatic discharge voltages by using transmission line pulse method and least square error solution method. In present invention, we introduce a parasitic series resistance, Rs, into the equation which presents the correlation between the transmission line pulse method and human body model. The equation is then rewritten as electrostatic discharge voltage=electrostatic discharge current×(the human body equivalent resistance+the parasitic series resistance) We can obtain the optimal parasitic series resistance and electrostatic discharge voltage by using the least square error solution method.

Abstract: A method for fabricating salicide devices over a substrate is described. The substrate has a gate structure pair in which a first gate structure comprises a first gate and a first stuffed film located on the first gate, and a second gate structure comprises a second gate and a second stuffed film located on the first gate. A first spacer is formed on the sidewall of the first gate structure. A second spacer is formed at the sidewall of the second gate structure. The first and the second stuffed films are removed. The second spacer is etched back so as to form a third spacer lower than the second gate. Salicide layers are formed upon the first and the second gates.

Abstract: An apparatus for loading wafers into horizontal quartz tube, the apparatus includes a base plate, holding plate, trolley main body and two supporting bases. The base plate has a plurality of stages, which is lifted by a loading rod and fixed atop thereon, for placing wafers. The holding plate has a plurality of fixing screws and altitude adjusting screws for supporting the base plate and changing an altitude of the base plate to match an altitude of wafer boat. The trolley main body, which supports the holding plate by supporting pillars, provides with a plurality of position holes for carrying the holding plate and moving the base plte. The two supporting bases are connected by a solid plate, whose both ends are respectively attached at hollows formed at the middle of each of the two supporting bases. The two supporting bases are provided with a pair of slide bearings on either side of the solid plate.

Abstract: A method of manufacturing the buried contact window of an SRAM cell. The method includes the steps of first providing a first conductive type substrate that has an isolating structure and a gate thereon. The gate comprises a gate oxide layer, a polysilicon layer and a sacrificial layer. Next, a heavily doped region of a second conductive type is formed in the substrate between the device isolating structure and the gate terminal. The heavily doped region acts as a buried contact window. Thereafter, a metal silicide layer is formed over the heavily doped region so that the two are electrically coupled. Next, the sacrificial layer is removed, and then a conductive layer that includes a polysilicon layer and a tungsten silicide layer is formed over the substrate. Subsequently, the conductive layer is patterned to form a conductive line layer and a gate stack.

Abstract: A fabrication process for a multi-layer photomask. A transparent substrate is provided. An anti-reflecting layer is formed on the substrate. First blinding blocks are formed on the anti-reflecting layer by defining a first blinding layer. A transparent layer is formed along the profile of the structure surface described above. Second blinding blocks are formed on the transparent layer between the first blinding blocks by defining a second blinding layer, wherein a part of the transparent layer on the first blocks is exposed.

Abstract: A FET is formed that occupies a reduced surface area on a substrate because it incorporates elevated source/drain contacts provided at least partially over the field oxide regions. A silicon nitride mask is formed over the substrate and the mask is used for defining field oxide regions. Trenches are etched on either side of the mask and then thermal oxidation grows field oxide regions in the trenches so that the surface of the field oxide regions are approximately even with the original surface of the substrate. With the silicon nitride mask still in place, polysilicon is deposited over the substrate. The device is then planarized to remove the polysilicon from surfaces of the substrate, exposing the surface of the mask and leaving polysilicon structures on the field oxide regions on either side of mask. The mask is stripped and a layer of silicon is deposited over the polysilicon structures and on the active device region of the substrate, where the deposited silicon is epitaxial.

Abstract: Fabricating a semiconductor memory device on a substrate having a transfer transistor formed thereon includes forming a first insulating layer over the transfer transistor, an etching protection layer over the first insulating layer, a second insulating layer over the etching protection layer, and a stacked layer over the second insulating layer, wherein the stacked layer has a recess therein disposed above a source/drain region of the transistor and exposing a portion of the second insulating layer. A third insulating layer is formed around the periphery of the recess and a fourth insulating layer is formed to fill the recess. Then the process includes removing the third insulating layer and the fourth insulating layer from the recess, and a portion of the second insulating layer directly below the third insulating layer to form a cavity which does not expose the etching protection layer. A first conductive layer is then formed to fill the recess and the cavity, followed by removing the stacked layer.