Abstract: A TSV structure includes a through via connecting a first side and a second side of a wafer, a conductive layer which fills up the through via, a through via dielectric ring surrounding and directly contacting the conductive layer, a first conductive ring surrounding and directly contacting the through via dielectric ring as well as a first dielectric ring surrounding and directly contacting the first conductive ring and surrounded by the wafer.

Abstract: A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.

Abstract: A method for transferring patterns. After a patterned photoresist is formed on a substrate, the patterned photoresist is hardened, and the pattern of the hardened patterned photoresist is transferred into the substrate. Moreover, a popular method to harden is the silylation process, it is acceptable to only harder the top of the patterned photoresist or to harden both the top and the sidewall of the patterned photoresist. Besides, it is optional to change the thickness and the critical dimension of the patterned photoresist before it is hardened. Significantly, because the etch resistance of hardened patterned photoresist is higher than that of the non-hardened patterned photoresist, the method can improve any defect induced by etched photoresist during the pattern transferring process. Similarly, because a thinner non-hardened photoresist is available for the method, a smaller critical dimension of the patterned photoresist is available for the method while the photolithography technology being not improved.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.