Abstract: A method for producing an at least partially housed semiconductor wafer is provided. This method comprises the steps of providing a semiconductor wafer which has components on its upper face and providing a cover disc, the surface of which at least partially covers the semiconductor wafer. After functionalizing the surface of the cover disc to form a functional layer, the upper face of the semiconductor wafer and the surface of the cover disc are joined together, followed by activating the functional layer using simultaneous chemical bonding of the semiconductor wafer and the cover disc such that the cover disc forms a housing for the semiconductor wafer.

Abstract: A method for producing an at least partially housed semiconductor wafer (16) is provided. This method comprises the steps of providing a semiconductor wafer (16) which has components (28) on its upper face (20) and providing a cover disc (2), the surface (4) of which at least partially covers the semiconductor wafer (16). After functionalizing the surface (4) of the cover disc (2) to form a functional layer (10), the upper face (20) of the semiconductor wafer (16) and the surface (4) of the cover disc (2) are joined together, followed by activating the functional layer (10) using simultaneous chemical bonding of the semiconductor wafer (16) and the cover disc (2) such that the cover disc (2) forms a housing for the semiconductor wafer (16).

Abstract: A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.

Abstract: A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.

Abstract: The invention relates to an electronic component having a GaAs semiconductor substrate (HS), semiconductor components (BE) being implemented on the front side thereof, and the back side thereof having a multilayer backside metallization (RM), wherein an advantageous construction of the layer sequence of the backside metallization is proposed, the backside metallization in particular comprising an Au layer as a bonding layer.

Abstract: For an HEMT component, in particular on the basis of GaN, it is proposed, for the purpose of reducing field spikes in the conduction channel, in a partial section of the conduction channel between gate electrode and drain electrode, to set the sheet resistance of the conduction channel such that it is higher than in adjacent regions. Various measures for subsequently increasing the sheet resistance in an area-selective manner are specified.

Abstract: The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Abstract: For an HEMT component, in particular on the basis of GaN, it is proposed, for the purpose of reducing field spikes in the conduction channel, in a partial section of the conduction channel between gate electrode and drain electrode, to set the sheet resistance of the conduction channel such that it is higher than in adjacent regions. Various measures for subsequently increasing the sheet resistance in an area-selective manner are specified.

Abstract: The invention relates to an electronic component having a GaAs semiconductor substrate (HS), semiconductor components (BE) being implemented on the front side thereof, and the back side thereof having a multilayer backside metallization (RM), wherein an advantageous construction of the layer sequence of the backside metallization is proposed, the backside metallization in particular comprising an Au layer as a bonding layer.

Abstract: The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Abstract: The production of a microelectronic component, particularly a pHEMT, having a T-shaped gate electrode in a double-recess structure uses a production method for self-adjusting alignment of the two recesses of the double-recess structure and of the gate foot of the gate electrode.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.

Abstract: A method for the production of individual integrated circuit arrangements from a wafer composite is disclosed, whereby the wafer is fixed with the component side (FS) on a support, the individual circuit arrangements (21) are separated on the support body by the etching of separating trenches (27) and individually lifted from the support body. The semiconductor substrate (20) is reduced in thickness during the fixing of the wafer to the support body, preferably to a substrate thickness of less than 100 ?m. A reverse face metallization (31) is deposited on the back face (RS) of the thinned substrate, preferably after separation of the circuit arrangements on the support body.

Abstract: Methods are specified for producing passive components on a substrate, which methods permit, with a low outlay and a good yield, the production of different components, in particular high-resistance and low-resistance resistor elements and/or capacitor elements having a higher and those having a lower capacitance per unit length on a substrate. In this case, lift-off processes can largely be dispensed with, particularly in the case of critical patternings, and selective dry- and/or wet-chemical etching can be effected.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.

Abstract: A hetero-bipolar transistor on Ga—As basis which has an advantageous design and to a method for producing the same which allows production of inexpensive and long-term stable components.

Abstract: The invention relates to a method for production of an integrated limiter. The integrated limiter with PIN diodes has the following structure: at least one PIN diode is disposed on a highly conductive n+substrate in a first level, at least one resistor is disposed in a second level, at least one capacitor is disposed in a third level, connecting metallization is applied on the third level and the levels are interconnected as an integrated limiter.

Abstract: In order to fabricate a semiconductor component having a contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T gate, a method is described in which a self-aligning positioning of gate base and gate head is effected by means of a spacer produced on a material edge.