Abstract: The method for forming a first electrodes of capacitors on a semiconductor substrate includes the steps as follows. At first, a first dielectric layer is formed. A portion of the first dielectric layer is then removed to define contact holes. A first conductive layer is formed within the contact holes and over the first dielectric layer. A second dielectric layer is formed over the first conductive layer. A portion of the second dielectric layer is removed to define the shape of the first electrodes. A second conductive layer is formed over the second dielectric layer and the first conductive layer. A first rugged silicon layer is formed over the second conductive layer. A third dielectric layer is then formed over the first rugged silicon layer. A portion of the third dielectric layer, of the first rugged silicon layer, and of the second conductive layer is removed to define capacitor area. The second dielectric layer is removed and a second rugged silicon layer is formed over the substrate.

Abstract: A method for measuring the extent of the kink effect of a transistor is disclosed herein. The aforementioned method includes the following steps. The first, generate a simulated drain current versus a gate voltage according to the transistor. Secondary, generate a drain current versus the gate voltage. Finally, integrate a difference between the simulated drain current and the drain current by the gate voltage.

Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.