Abstract: A wafer support member that can move in the same chamber after a film has been formed on a wafer and enable processing of the film-formed wafer and a semiconductor manufacturing apparatus including the wafer support member are provided. The wafer support plate 10 includes a flat portion 1 configured to support a wafer W and an outer circumferential protruding portion 2, being disposed in a surrounding shape on an outer circumference of the flat portion 1 and being formed with a larger thickness than the wafer W. The flat portion 1 includes a perforated support portion 1A and an annular support portion 1B. The annular support portion 1B is disposed outside of the perforated support portion 1A and supports an outer circumferential end portion Wo of the wafer W.

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Abstract: A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

Abstract: A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

Abstract: A probe position monitoring structure includes a first common line and a contact portion configured for being directly contacted with a probe. The contact portion includes a first zigzag structure, and a first end of the first zigzag structure is directly connected with the first common line. A method of monitoring a position of a probe includes the following steps. The probe position monitoring structure is provided. The first zigzag structure is directly contacted with a first probe. A resistance measurement is performed to measure a resistance of a portion of the first zigzag structure located between the first probe and the first end for monitoring a position of the first probe.

Abstract: A probe position monitoring structure includes a first common line and a contact portion configured for being directly contacted with a probe. The contact portion includes a first zigzag structure, and a first end of the first zigzag structure is directly connected with the first common line. A method of monitoring a position of a probe includes the following steps. The probe position monitoring structure is provided. The first zigzag structure is directly contacted with a first probe. A resistance measurement is performed to measure a resistance of a portion of the first zigzag structure located between the first probe and the first end for monitoring a position of the first probe.

Abstract: A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

Abstract: A semiconductor device having a transistor with fin structure includes a channel layer that is disposed over a substrate and is connected to the substrate via a semiconductor layer, a source layer that is disposed on a first side surface of the channel layer over the substrate and is separated from the substrate via a first insulating layer, a drain layer that is disposed on a second side surface of the channel layer opposite to the first side surface over the substrate and is separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed over the channel layer and a second portion which is disposed between the substrate and the channel layer and whose third side surface or fourth side surface faces the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

Abstract: A voltage regulator includes an operational amplifier, a first transistor, a second transistor, a capacitor and a current sink circuit. The operational amplifier outputs a control voltage according to an amplified differential voltage between a first input terminal and a second input terminal of the operational amplifier. The first transistor includes a control terminal receiving the control voltage, a first terminal coupled to a supply terminal, a second terminal providing an output voltage, and a bulk terminal. The second transistor includes a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The capacitor includes a first terminal coupled to the bulk terminal of the first transistor, and a second terminal receiving the output voltage. The current sink circuit generates a feedback voltage according to the output voltage and output the feedback voltage to the operational amplifier.

Abstract: A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

Abstract: A bottle cap is disclosed. The bottle cap includes a cap body having a cover plate and a cylinder part integral with the cover plate. A stopper member protrudes from an inner surface of the cover plate. The stopper member includes a sealing part supported by a support structure integral with the cover plate. An annular guiding plate protrudes from a sidewall surface of the cylinder part and is inclined toward the stopper member to engage with the sealing part.

Abstract: A mask structure for a deposition device includes first segments and second segments. The first segments are arranged in a direction surrounding a central axis and separated from one another. The second segments are disposed above the first segments. Each of the second segments overlaps two of the first segments adjacent to each other in a vertical direction parallel to an extending direction of the central axis. A deposition device includes a process chamber, a stage, and the mask structure. The stage is at least partially disposed in the process chamber and includes a holding structure of a substrate. The mask structure is disposed in the process chamber, located over the stage, and covers a peripheral region of the substrate to be held on the stage. An operation method of the deposition device includes horizontally adjusting positions of the first segments and the second segments respectively between different deposition processes.

Abstract: A mask structure for a deposition device includes first segments and second segments. The first segments are arranged in a direction surrounding a central axis and separated from one another. The second segments are disposed above the first segments. Each of the second segments overlaps two of the first segments adjacent to each other in a vertical direction parallel to an extending direction of the central axis. A deposition device includes a process chamber, a stage, and the mask structure. The stage is at least partially disposed in the process chamber and includes a holding structure of a substrate. The mask structure is disposed in the process chamber, located over the stage, and covers a peripheral region of the substrate to be held on the stage. An operation method of the deposition device includes horizontally adjusting positions of the first segments and the second segments respectively between different deposition processes.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.

Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate, a gate electrode disposed over the first semiconductor area and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a second semiconductor area of a second conductive type disposed, in the surface layer portion of the semiconductor substrate, between the gate electrode and the dummy gate electrode, and an interconnect connected to the second semiconductor area, wherein a concentration of carrier of a first carrier type in the semiconductor substrate under the dummy gate electrode and alongside the second semiconductor area is lower than a concentration of majority carrier in the first semiconductor area, the first carrier type being a same carrier type as the majority carrier.

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Abstract: A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film.