Patents Assigned to UNITED TEST AND ASSEMBLY CENTER
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Patent number: 10403592Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: October 6, 2017Date of Patent: September 3, 2019Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
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Patent number: 9786625Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: July 20, 2015Date of Patent: October 10, 2017Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
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Publication number: 20160211196Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: ApplicationFiled: January 27, 2016Publication date: July 21, 2016Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Danny RETUTA, Hien Boon TAN, Anthony Yi Sheng SUN, Mary Annie CHEONG
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Patent number: 9281218Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: GrantFiled: August 29, 2007Date of Patent: March 8, 2016Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Danny Retuta, Hien Boon Tan, Anthony Yi Sheng Sun, Mary Annie Cheong
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Patent number: 9165878Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: December 2, 2013Date of Patent: October 20, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yong Bo Yang, Chun Hong Wo
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Patent number: 9142487Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: January 9, 2013Date of Patent: September 22, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Patent number: 9136142Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: April 21, 2014Date of Patent: September 15, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Patent number: 9117808Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.Type: GrantFiled: April 21, 2014Date of Patent: August 25, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock Toh, Kriangsak Sae Le
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Patent number: 9087777Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: March 14, 2013Date of Patent: July 21, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
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Patent number: 9023690Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.Type: GrantFiled: November 19, 2012Date of Patent: May 5, 2015Assignee: United Test and Assembly CenterInventors: Antonio Bambalan Dimaano, Jr., Nathapong Suthiwongsunthorn, Yong Bo Yang
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Publication number: 20150102478Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: United Test and Assembly Center Ltd.Inventors: Nathapong SUTHIWONGSUNTHORN, John Ducyao BELERAN, Serafin Padilla PEDRON, JR.
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Patent number: 8916422Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.Type: GrantFiled: March 15, 2013Date of Patent: December 23, 2014Assignee: United Test and Assembly Center Ltd.Inventor: Chuen Khiang Wang
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Patent number: 8860079Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.Type: GrantFiled: May 9, 2012Date of Patent: October 14, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
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Publication number: 20140264835Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventor: Chuen Khiang WANG
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Publication number: 20140264789Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
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Publication number: 20140264792Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: December 2, 2013Publication date: September 18, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Yong Bo YANG, Chun Hong WO
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Patent number: 8829666Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die.Type: GrantFiled: November 14, 2011Date of Patent: September 9, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
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Patent number: 8816482Abstract: A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached to the semiconductor die is below a portion of the leadframe that enters the encapsulant.Type: GrantFiled: December 9, 2008Date of Patent: August 26, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Saravuth Sirinorakul, Kasemsan Kongthaworn
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Publication number: 20140227832Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
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Publication number: 20140225242Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Chin Hock TOH, Kriangsak Sae LE