Patents Assigned to United Test & Assembly Center Limited
  • Patent number: 8288862
    Abstract: A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: October 16, 2012
    Assignee: United Test & Assembly Center Limited
    Inventors: Wang Chuen Khiang, Koh Yong Chuan, Fong Kok Chin
  • Patent number: 7816775
    Abstract: A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: October 19, 2010
    Assignee: United Test and Assembly Center Limited
    Inventors: Chuen Khiang Wang, Hao Liu, Hien Boon Tan, Clifton Teik Lyk Law, Rahamat Bidin, Anthony Yi Sheng Sun
  • Patent number: 7504715
    Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 17, 2009
    Assignee: United Test & Assembly Center Limited
    Inventor: Wang Chuen Khiang
  • Patent number: 7443041
    Abstract: A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are located on the surface of the microchip devices. Electrical contacts on the microchip device surface are accessible through the aperture in order to electrically connect the electrical contacts with the external electrical contacts of the interposer. The aperture is divided into at least two openings or aperture regions, separated by a bridge. This facilitates the handling of the interposer.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 28, 2008
    Assignee: United Test & Assembly Center Limited
    Inventor: Wang Chuen Khiang
  • Publication number: 20070132081
    Abstract: A semiconductor package including a first substrate having a die receiving area, a first adhesive layer, a window opening, and a plurality of conductive traces, a first semiconductor die having two sides and with an electrically active side mounted to the substrate through the first adhesive layer, a second adhesive layer having a first side attached to an electrically inactive side of the first semiconductor die, a second substrate having a die receiving area and a plurality of conductive traces and terminals, a last adhesive layer having a first side attached to a side of the second substrate with the terminals, a last semiconductor die having two sides and with an electrically inactive side being mounted to the second side of the third adhesive layer, and an electrically active side being electrically coupled to the conductive traces of the first or second substrate directly or through a redistribution device, and an encapsulant to encapsulate the semiconductor dies and electrical coupling, and signal tran
    Type: Application
    Filed: March 3, 2005
    Publication date: June 14, 2007
    Applicant: UNITED TEST AND ASSEMBLY CENTER LIMITED
    Inventors: Chuen Khiang Wang, Hien Boon Tan, Koon Hwee Joanne Teo, Sin Nee Song, Koon Lua
  • Publication number: 20070013040
    Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.
    Type: Application
    Filed: September 21, 2006
    Publication date: January 18, 2007
    Applicant: UNITED TEST & ASSEMBLY CENTER LIMITED
    Inventor: Wang Khiang
  • Patent number: 7129115
    Abstract: A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are located to the surface of the microchip devices. Electrical contacts on the microchip device surface are accessible through the aperture in order to electrically connect the electrical contacts with the external electrical contacts of the interposer. The interposer includes separate openings or aperture regions, in particular separated by a bridge, which extend from the interposer surface where the external contacts are located into the interposer. This facilitates the handling of the finalized package and allows for satisfactory filling of the aperture with filling material.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 31, 2006
    Assignee: United Test & Assembly Center Limited
    Inventor: Wang Chuen Khiang
  • Patent number: 7023076
    Abstract: A semiconductor package, containing two or more IC devices. The IC devices are oriented in the same manner and at least two IC devices are separated by a die paddle that is attached to the active face of one of the IC devices, inward of the electrical contact areas.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: April 4, 2006
    Assignee: United Test & Assembly Center Limited
    Inventor: Wang Chuen Khiang
  • Publication number: 20040140475
    Abstract: Two substrates each carrying MEMS or MOEMS structures are bonded face to face and interconnected to form a compact surface-mountable package.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 22, 2004
    Applicant: United Test & Assembly Center Limited
    Inventors: Yi-Sheng Sun, Desmond Chong Yok Rue, Rahul Kapoor
  • Publication number: 20040140557
    Abstract: A MEMS/MOEMS device is provided on a first substrate which is bonded to a second substrate to form a package. Interconnections may be provided via the second substrate and an hermetic seal may be formed to protect the MEMS/MOEMS device from outgassing.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 22, 2004
    Applicant: United Test & Assembly Center Limited
    Inventors: Yi-Sheng Sun, Desmond Chong Yok Rue, Rahul Kapoor
  • Publication number: 20040012079
    Abstract: A semiconductor package, containing two or more IC devices. The IC devices are oriented in the same manner and at least two IC devices are separated by a die paddle that is attached to the active face of one of the IC devices, inward of the electrical contact areas.
    Type: Application
    Filed: January 21, 2003
    Publication date: January 22, 2004
    Applicant: United Test & Assembly Center Limited of Singapore
    Inventor: Wang Chuen Khiang
  • Publication number: 20030197284
    Abstract: A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.
    Type: Application
    Filed: February 11, 2003
    Publication date: October 23, 2003
    Applicant: United Test & Assembly Center Limited
    Inventors: Wang Chuen Khiang, Koh Yong Chuan, Fong Kok Chin