Abstract: A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.

Abstract: A ball-implantation method and a system applying the method are provided. To begin with, solder balls are implanted onto a flux applied to each of the ball pads on a substrate plate. Then, a vibration force of preset magnitude is exerted on the substrate plate, inducing vibration and causing any solder balls that have deviated from positions corresponding to the ball pads exposed from the openings of a solder mask provided on the substrate plate to return to the correct orientation and be kept therein by the vibration force and gravity. Subsequently, the ball implantation process is completed using a reflow process to solder the implanted solder balls. Using this method and the system thereof, the problem of missing or misaligned solder balls that occurs after the reflow process is solved, thereby dispensing with rework and improving the production yield and product reliability.

Abstract: A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.

Abstract: A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.

Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Abstract: The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

Abstract: A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

Abstract: The present invention is to provide a printed circuit board, which comprises a substrate, a conductive pattern disposed on a surface of said substrate and a solder mask coated on the surface of said substrate and covered over the conductive pattern. The conductive pattern has a bonding pad. The solder mask has an opening corresponding in location to the bonding pad such that a portion of the bonding pad is exposed outside. A space is left between said solder mask and said bonding pad and is communicated with the opening. Whereby, a solder ball can be received in the opening and the space and electrically connected to the bonding pad, such that the solder ball is held on the printed circuit board securely.

Abstract: A low-profile optically-sensitive semiconductor device is disclosed which includes a substrate with an opening. A cover plate is bonded to a first surface of the substrate in such a manner that a optically-sensitive semiconductor chip is adhered thereto via the opening of the substrate. Right after the semiconductor chip is electrically coupled to the substrate, a first encapsulant with a through hole connected with the opening of the substrate, is formed on the second surface of the substrate. A sealing plate is then attached to the first encapsulant to seal the through hole, so as to hermetically separate the semiconductor chip from the atmosphere. On the first surface of the substrate, a second encapsulant is formed such that ends of the conductive elements and an outer surface of the cover plate are exposed to and flush with a top surface of the second encapsulant.

Abstract: A packaging process for a semiconductor package is proposed, in which a plurality of conductive elements disposed on a substrate are electrically connected to the substrate and encapsulated by a first encapsulant formed on the substrate. Further, a semiconductor chip having a plurality of bond pads is mounted on a top surface of the first encapsulant and is electrically connected to the substrate through the bond pads being electrically connected to the corresponding conductive elements. Moreover, as the conductive elements have ends thereof coplanarly formed with the top surface of the first encapsulant, quality of the electrical connection between the chip and the conductive elements can be assured. In addition, as the conductive elements for electrically connecting the chip to the substrate are disposed on the substrate, the packaging cost can be reduced and quality of the packaged product can be improved.

Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Abstract: A low-profile optically-sensitive semiconductor device is disclosed which includes a substrate with an opening. A cover plate is bonded to a first surface of the substrate in such a manner that a optically-sensitive semiconductor chip is adhered thereto via the opening of the substrate. Right after the semiconductor chip is electrically coupled to the substrate, a first encapsulant with a through hole connected with the opening of the substrate, is formed on the second surface of the substrate. A sealing plate is then attached to the first encapsulant to seal the through hole, so as to hermetically separate the semiconductor chip from the atmosphere. On the first surface of the substrate, a second encapsulant is formed such that ends of the conductive elements and an outer surface of the cover plate are exposed to and flush with a top surface of the second encapsulant.

Abstract: A semiconductor device without used of a chip carrier and method for making the same are proposed, in which a semiconductor chip has an active surface for disposing a plurality of conductive elements and forming a first encapsulant thereon, and a non-active surface for forming a second encapsulant thereon. The conductive elements are used to electrically connect the semiconductor chip to external devices. The first encapsulant is used to prevent the active surface from exposure to the atmosphere and encapsulate the conductive elements, for allowing one end of each of the conductive elements to be exposed to outside of the first encapsulant and coplanarly positioned with an outer surface of the first encapsulant. The second encapsulant together with the first encapsulant are able to provide sufficient structural strength for the semiconductor chip.

Abstract: A low-profile semiconductor device is disclosed which includes a substrate having a base layer formed with at least a hole and a plurality of conductive traces arranged on the base layer. A semiconductor die is attached to the base layer of the substrate opposite to the conductive traces and electrically connected to the conductive traces by a plurality of first conductive elements passing through the hole of the base layer. A plurality of second conductive elements are arrayedly connected to the terminal of each of the conductive traces for providing externally electrical connection to the semiconductor die. The semiconductor die is encapsulated by a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted. A second encapsulant is formed on the surface of the substrate on which the conductive traces are arranged to completely encapsulate the conductive traces, first conductive elements and the hole.

Abstract: A chip scale packaging method is used to package a single-sided substrate and one or more semiconductor chips. The nonconductive surface of the substrate is provided with one or more chip-implanting adhesive areas by stenciling. The adhesive areas are provided with one or more through holes. The chips are implanted in the adhesive areas of the substrate such that the active surface of each chip is in contact with the adhesive area, and that the bonding pads of the active surface of the chip are corresponding in location to the through holes. Upon completion of the chip implantation, the substrate and the implanted chips are heated under pressure before the bonding pads are connected with the conductive surface of the substrate by a plurality of metal bonding wires. The chips and the through holes are subsequently provided with a passivation layer. Finally, the conductive surface of the substrate is implanted with a plurality of spherical bonding points in a grid array fashion.