Patents Assigned to Unitive International
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Patent number: 8294269Abstract: An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 ?m. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof.Type: GrantFiled: December 8, 2010Date of Patent: October 23, 2012Assignee: Unitive InternationalInventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Patent number: 7879715Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.Type: GrantFiled: October 8, 2007Date of Patent: February 1, 2011Assignee: Unitive International LimitedInventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Patent number: 7839000Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.Type: GrantFiled: May 8, 2009Date of Patent: November 23, 2010Assignee: Unitive International LimitedInventors: J. Daniel Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne
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Patent number: 7834454Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.Type: GrantFiled: August 20, 2008Date of Patent: November 16, 2010Assignee: Unitive International LimitedInventors: Glenn A. Rinne, J. Daniel Mis
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Patent number: 7665652Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.Type: GrantFiled: May 3, 2004Date of Patent: February 23, 2010Assignee: Unitive International LimitedInventors: J. Daniel Mis, Kevin Engel
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Patent number: 7659621Abstract: Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.Type: GrantFiled: February 27, 2006Date of Patent: February 9, 2010Assignee: Unitive International LimitedInventor: Glenn A. Rinne
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Patent number: 7579694Abstract: Bumping a substrate having a metal layer thereon may include forming a barrier layer on the substrate including the metal layer and forming a conductive bump on the barrier layer. Moreover, the barrier layer may be between the conductive bump and the substrate, and the conductive bump may be laterally offset from the metal layer. After forming the conductive bump, the barrier layer may be removed from the metal layer thereby exposing the metal layer while maintaining a portion of the barrier layer between the conductive bump and the substrate. Related structures are also discussed.Type: GrantFiled: June 2, 2006Date of Patent: August 25, 2009Assignee: Unitive International LimitedInventors: Jong-Rong Jan, Tsai-Hua Lu, Sao-Ling Chiu, Ling-Chen Kung
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Patent number: 7550849Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.Type: GrantFiled: June 20, 2007Date of Patent: June 23, 2009Assignee: Unitive International LimitedInventors: J. Daniels Mis, Dean Zehnder
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Patent number: 7547623Abstract: Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer. In addition, a solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer. In addition, a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer with portions of the under bump seed metallurgy layer being free of the copper layer. Accordingly, the under bump seed metallurgy layer may be between the copper layer and the electronic substrate, and the copper layer may be between the under bump seed metallurgy layer and the nickel layer. Related structures are also discussed.Type: GrantFiled: June 29, 2005Date of Patent: June 16, 2009Assignee: Unitive International LimitedInventors: J. Daniel Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne
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Patent number: 7531898Abstract: An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad. In addition, an insulating layer may be provided on the substrate, on the conductive line, and on edge portions of the conductive pad. The insulating layer may have a hole therein exposing a central portion of the conductive pad, and a first segment of a perimeter of the hole may substantially define an arc of a circle around the central portion of the conductive pad. A second segment of the perimeter of the hole may substantially deviate from the circle around the central portion of the conductive pad, and the second segment of the perimeter of the hole may be adjacent a connection between the conductive line and the conductive pad.Type: GrantFiled: November 9, 2005Date of Patent: May 12, 2009Assignee: Unitive International LimitedInventors: William E. Batchelor, Glenn A. Rinne
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Patent number: 7495326Abstract: An electronic device may include first, second, and third substrates wherein the second electronic substrate is between the first and second electronic substrates. A first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. In addition or in an alternative, an electronic device may include a printed circuit board, a first electronic substrate on the printed circuit board, a second electronic substrate on the first electronic substrate, and a third electronic substrate on the second electronic substrate. More particularly, the first electronic substrate may be between the printed circuit board and the second electronic substrate, and the second electronic substrate may be between the first and third electronic substrates.Type: GrantFiled: October 21, 2003Date of Patent: February 24, 2009Assignee: Unitive International LimitedInventor: Glenn A. Rinne
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Patent number: 7427557Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.Type: GrantFiled: March 9, 2005Date of Patent: September 23, 2008Assignee: Unitive International LimitedInventors: Glenn A. Rinne, J. Daniel Mis
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Patent number: 7297631Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.Type: GrantFiled: September 14, 2005Date of Patent: November 20, 2007Assignee: Unitive International LimitedInventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Patent number: 7244671Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.Type: GrantFiled: June 29, 2004Date of Patent: July 17, 2007Assignee: Unitive International LimitedInventors: J. Daniels Mis, Dean Zehnder
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Patent number: 7213740Abstract: A liquid prime mover can be used to position a component on a substrate. For example, a liquid material can be provided on the substrate adjacent the component such that the component has a first position relative to the substrate. A property of the liquid material can then be changed to move the component from the first position relative to the substrate to a second position relative to the substrate. Related structures are also discussed.Type: GrantFiled: August 26, 2005Date of Patent: May 8, 2007Assignee: Unitive International LimitedInventor: Glenn A. Rinne
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Patent number: 7156284Abstract: Methods of bonding two components may include positioning the components relative to one another to obtain a desired orientation. Once the desired orientation is obtained, the components can be bonded in the desired orientation with metal wherein a temperature of both components is maintained below a melting temperature of the metal while bonding. Related structures are also discussed.Type: GrantFiled: March 2, 2004Date of Patent: January 2, 2007Assignee: Unitive International LimitedInventors: Glenn A. Rinne, Krishna K. Nair
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Patent number: 7049216Abstract: Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.Type: GrantFiled: October 13, 2004Date of Patent: May 23, 2006Assignee: Unitive International LimitedInventor: Glenn A. Rinne
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Patent number: 6960828Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.Type: GrantFiled: June 23, 2003Date of Patent: November 1, 2005Assignee: Unitive International LimitedInventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Electroplating methods including maintaining a determined electroplating voltage and related systems
Patent number: 6793792Abstract: Methods for electroplating metal can include passing an electrical current through a conductive surface and an electroplating solution adjacent the conductive surface. An electroplating voltage for the conductive surface and the electroplating solution can be determined based on the electrical current through the conductive surface and the electroplating solution adjacent the conductive surface. The determined electroplating voltage can then be maintained while electroplating the metal from the electroplating solution on the conductive surface. Related systems are also discussed.Type: GrantFiled: January 11, 2002Date of Patent: September 21, 2004Assignee: Unitive International Limited CuracoInventors: Curtis Grant Jones, William Boyd Rogers, Glenn A. Rinne -
Publication number: 20020074381Abstract: Methods of bonding two components may include positioning the components relative to one another to obtain a desired orientation. Once the desired orientation is obtained, the components can be bonded in the desired orientation with metal wherein a temperature of both components is maintained below a melting temperature of the metal while bonding. Related structures are also discussed.Type: ApplicationFiled: December 14, 2001Publication date: June 20, 2002Applicant: Unitive International LimitedInventors: Glenn A. Rinne, Krishna K. Nair