Abstract: There is provided an trapped ion processor comprising a DAC chamber, an ASIC, a digital control line between the DAC chamber and the ASIC and an analogue control line between the DAC chamber and the ASIC. The ASIC comprises a plurality of channels, each channel comprising a DC electrode, a first analogue memory cell and a second analogue memory cell. The DAC chamber comprises a DAC configured to generate an analogue signal and a DAC controller configured to generate timing control signals, the timing control signals comprising one or more sample timing signals to control when the analogue signal is sampled, as a voltage signal, by one or more of the plurality of the channels, and one or more synchronisation signals to control when the sampled voltage signal is applied to the respective DC electrode.

Abstract: According to the invention, there is provided a timing system for an ion trap quantum computer comprising a clock outputting a timing signal of period t, a plurality of delay lines coupled to the clock and each configured to input a different delay of less than t and a delay selection mechanism configured to select the delay wherein the delay by each of the delay lines is a different fraction of the period t.

Abstract: According to the invention there is provided an ion trap comprising a plurality of electrodes forming an ion trap, a plurality of DACs, each DAC being configured to control an electrode, a clock signal generator, configured to transmit a clock signal to each electrode, a multiplexer configured to stop or transmit the clock signal from the clock signal generator to one or more of the DACs and a clock signal controller configured to control, by the multiplexer, the clock signal to DACs.

Abstract: A surface ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs control the electrodes configured to trap an ion in a first area and a second set of DACs control the electrodes configured to trap an ion in a second area wherein the first set of DACs are configured to operate with low noise and low bandwidth and the second set of DACs are configured to operate with a high bandwidth and high noise.