Patents Assigned to Universiadad de Granada
  • Publication number: 20120113730
    Abstract: A memory element includes a MOS transistor having a drain, a source and a body region covered by an insulated gate, wherein the thickness of the body region is divided into two distinct regions separated by a portion of an insulating layer extending parallel to the plane of the gate.
    Type: Application
    Filed: April 13, 2010
    Publication date: May 10, 2012
    Applicants: Centre National de la Recherche Scientifique, Universiadad de Granada
    Inventors: Sorin Ioan Cristoloveanu, Noel Rodriguez, Francisco Gamiz