Abstract: At least a method and an apparatus are presented for determining a coded modulation scheme, the coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping. Two or more candidate modulation mappings and two or more candidate parity-check equations are determined defining the at least one non-binary error correcting code, a candidate set comprising a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being evaluated for a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value. One candidate modulation mapping and at least one candidate parity-check equation are selected according to an optimization criterion applied to the one or more metrics.

Abstract: A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.

Abstract: A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Abstract: Embodiments of the invention provide a decoder for determining an estimate of an encoded signal, the decoder comprising one or more variable node processing units (23) and one or more check node processing units (25) configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with said symbol, wherein the decoder comprises: at least one vector permutation unit (24) configured to receive a set of at least three variable node messages comprising variable node components from at least one variable node processing unit and to generate permuted messages depending on a plurality of the reliability metrics comprised in said variable node components, the variable node messages being sorted according to an order of the reliability metrics; and at least one check node processing unit (25-1) configured to: calculate at two or more elementary check node processors (26) a set of syndromes from said at least three permuted messages

Abstract: Embodiments of the invention provide a check node processing unit implemented in a decoder for decoding a signal, the check node processing unit being configured to receive at least three input messages and to generate at least one output message, wherein the check node processing unit comprises: a syndrome calculator (31) configured to determine a set of syndromes from said at least three input messages using at least two elementary check node processors (311), each syndrome comprising a symbol, a reliability metric associated with said symbol, and a binary vector; a decorrelation unit (33) configured to determine, in association with at least an output message, a set of candidate components from said set of syndromes, each candidate component comprising a symbol and a reliability metric associated with said symbol, said set of candidate components comprising one or more pairs of components comprising a same symbol; and a selection unit (35) configured to determine at least an output message by selecting

Abstract: Embodiments of the invention provide a device for determining a coded modulation scheme, said coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping, wherein the device comprises: a calculation unit (31) configured to determine one or more candidate modulation mappings and one or more candidate parity-check equations defining said at least one non-binary error correcting code, each set of a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being defined by a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value; and a selection unit (35) configured to select one candidate modulation mapping and at least one candidate parity-check equation according to an optimization criterion applied to said one or more metrics.

Abstract: Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some of

Abstract: A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a nrepresentation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check N node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.

Abstract: The invention concerns a method for transmitting symbols of non binary error correcting code words via a transmission channel. The method comprises a first modulation associating each code word symbol of p bits with a sequence of at least 2p chips from 2p possible sequences, a second modulation to modulate the phase or amplitude of a carrier signal with the sequences associated with the code words, and a step of transmitting the modulated carrier signal via said transmission channel. According to the invention, the first modulation is a spread spectrum modulation of the cyclic code shift keying type using a basic pseudo-random sequence of at least 2p chips, the possible 2p sequences being obtained by a circular shift of the basic pseudo-random sequence and a cyclic prefix is inserted into each symbol to be transmitted.

Abstract: A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm? elements sorted in said ascending or descending order, nm? being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

Abstract: An encoder comprises a first and a second input, and a first and a second output, and the encoder comprises a selection block suitable for selecting a more significant bit and a less significant bit. The encoder comprises a switching block suitable for connecting the first input to the first output, and the second input to the second output, the switching block being suitable for being switched in order to connect the first input to the second output and the second input to the first output, when the selection block has selected a less significant bit and a more significant bit. A decoder, a storage medium and an electronic system is also disclosed.

Abstract: The present invention is related to a method for detecting at least one chemical analyte vapour in a gaseous environment comprising the steps of: providing a fibre-based electrochemical sensor, said fibre-based sensor comprising at least one type of composite fibres, said type of composite fibres comprising a co-continuous phase blend comprising a first and a second continuous polymer phase, the first polymer phase being sensitive to the chemical analyte vapour to be detected in use, wherein said first polymer phase comprises a dispersion of carbon nanotubes at a concentration above the percolation threshold and wherein the chemical analyte is soluble in said first polymer phase; measuring the initial electrical conductivity of the fibre-based sensor; bringing said fibre-based sensor into contact with at least one chemical analyte to induce a modification of the electrical conductivity of the fibres; measuring the modification of the resulting electrical conductivity of said fibre-based sensor and correla

Abstract: The present invention is related to a polymer fibre-based PTC resistor comprising a co-continuous polymer phase blend, said blend comprising a first and a second continuous polymer phase, wherein the first polymer phase comprises a dispersion of carbon nanotubes at a concentration above the percolation threshold, said first polymer phase presenting a softening temperature lower than the softening temperature of the second polymer phase.

Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1,U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm, elements sorted in said ascending or descending order, nm, being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

Abstract: A method for reconfiguring a set (4) of components of an electronic circuit (2) provided with memory resources (6), the circuit (2) being connected to a network (8), is characterized in that it includes a step of downloading configuration data for the set (4) to the memory resources (6) of the electronic circuit (2) from a server (10) connected to the network (8).

Abstract: A router in which each of the input/output ports is associated with identifiers enabling each of the other input/output ports to locate it according to a code specific to each of them, comprising means for identifying in an incident packet a routing instruction indicating a forward identifier of the desired output port; and means for sending back the packet where the forward identifier is suppressed from the routing instruction and a return identifier is inserted therein.

Abstract: A decoder of LDPC codewords on GF(rq), using the iterative belief propagation algorithm comprises at least storing means to store a posteriori information on variables. Updating means updates the a posteriori information on variables, and computation means computes variables to constrain messages from a posteriori information on variables and variable to constraint messages from previous iteration. Computation means computes a constraint to variable messages from variable to constraint messages computed by the first computation means. Computation means updates the a posteriori information on variables. Shuffle means transfers the a posteriori information on variables to the first computation means, and shuffle means transfers information from the second computation means to the storing means. Compression-storage-decompression means constraint to variable messages. In one form, the invention concerns also corresponding method, computer program and system.