Abstract: The present invention relates to the production of gene sequences encoding chimerical membrane glycosyltransferases presenting an optimized glycosylation activity in cells transformed with the sequences, the gene sequences corresponding to the fusion: of a first nucleic acid coding for a C-terminal minimal fragment of the catalytic domain (CD) of the native full length glycosyltransferase, to a second nucleic acid coding for a transmembrane peptide comprising in its N-terminal region a cytoplasmic tail (CT) region located upstream from a transmembrane domain (TMD), itself located upstream of a stem region (SR), provided that at least one of these CT, TMD, SR peptides being different from the primary structure of the naturally occurring peptide counterparts present in the native glycosyltransferase from which is derived the CD fragment with optimal glycosyltransferase activity as defined above.

Abstract: The pulse train of a signal is modulated by a DPIM modulation involving a discrete random time parameter. A first processing is performed on the signal to deliver a sampled signal. A second processing is performed on the sampled signal, comprising a correlation processing including at least one elementary correlation processing with a correlation mask corresponding to the shape of at least part of a sampled pulse, and delivering second information items. A third processing is performed for detecting the pulses following a first pulse by taking account of the position of the first pulse, on packets of second information items, which are separated by a duration related to the discrete random parameter.

Abstract: An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal.

Abstract: The disclosure relates to a method for generating UWB waveforms, each comprising a sequence of pulses, the method comprising: generating consecutive elementary pulses having durations corresponding to setpoint durations and a constant amplitude, amplifying each elementary pulse separately as a function of a respective setpoint amplitude, and combining the amplified elementary pulses to obtain a waveform successively comprising each of the amplified alternately positive and negative, elementary pulses.

Abstract: The disclosure relates to an amplifier comprising a digital delta-sigma modulator, a quantifier receiving a signal supplied by a delta-sigma stage and supplying a quantified signal, and a power circuit supplying an output signal. The device comprises N state loops of a first type configured to send the output signal to adders of N delta-sigma stages of lower rank, each state loop of the first type comprising an analog low-pass filter for supplying a filtered output signal, and an analog to digital converter for supplying a digital filtered output signal.

Abstract: The present invention relates to the production of gene sequences encoding chimerical membrane glycosyltransferases presenting an optimized glycosylation activity in cells transformed with said sequences, said gene sequences corresponding to the fusion: of a first nucleic acid coding for a C-terminal minimal fragment of the catalytic domain (CD) of the native full length glycosyltransferase, to a second nucleic acid coding for a transmembrane peptide comprising in its N-terminal region a cytoplasmic tail (CT) region located upstream from a transmembrane domain (TMD), itself located upstream of a stem region (SR), provided that at least one of these CT, TMD, SR peptides being different from the primary structure of the naturally occurring peptide counterparts present in the native glycosyltransferase from which is derived the CD fragment with optimal glycosyltransferase activity as defined above.

Abstract: An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal.

Abstract: A digital processing device for a modulated signal, arranged at the input of a radio frequency receiver chain, suited in particular to a transmission system a direct sequence spread spectrum operation, comprising an analog-to-digital converter performing undersampling of the signal received, leading to an overlapping of the frequency range of the undersampled wanted signal by the frequency range of an interfering signal, demodulation means connected at the output of the analog-to-digital converter in order to bring the undersampled wanted signal back to baseband, a low pass filter connected at the output of the demodulation means and a filter matched to the spreading code used, and an additional filtering unit arranged between the low pass filter and the matched filter, for implementing a stochastic matched filtering operation to improve the signal-to-noise ratio at the input of the matched filter.

Abstract: An oscillator is provided that includes an oscillating structure generating an output signal with a frequency that drifts as a function of a parameter of its environment, and a compensation circuit coupled to the oscillating structure. The oscillating structure has a ring structure that includes delay cells looped together, and the compensation circuit supplies a compensation signal to the oscillating structure. The compensation signal varies as a function of changes in the parameter in order to compensate for the drift in the frequency of the generated signal. This makes it possible to compensate for oscillator temperature drifts in the absence of a regulation loop.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: The pulse train of a signal is modulated by a DPIM modulation involving a discrete random time parameter. A first processing is performed on the signal to deliver a sampled signal. A second processing is performed on the sampled signal, comprising a correlation processing including at least one elementary correlation processing with a correlation mask corresponding to the shape of at least part of a sampled pulse, and delivering second information items. A third processing is performed for detecting the pulses following a first pulse by taking account of the position of the first pulse, on packets of second information items, which are separated by a duration related to the discrete random parameter.

Abstract: The invention proposes a negative gain transconductance amplifier circuit (1) for capacitive load that includes: an RC serial circuit connected between an input terminal (E) of the amplifier circuit and a intermediate terminal (A); an amplification level connected between the intermediate terminal and an output terminal (S) designed to be connected to a capacitive load, and which includes: a first negative gain transconductance amplifier (2) connected via open loop between the intermediate terminal and the output terminal; a second negative gain transconductance amplifier (3) with characteristics that are notably identical to those of the first amplifier, connected via closed loop; its input and output are connected to the intermediate terminal via a resistance (R1).

Abstract: The invention proposes a negative gain transconductance amplifier circuit (1) for capacitive load that includes: an RC serial circuit connected between an input terminal (E) of the amplifier circuit and a intermediate terminal (A); an amplification level connected between the intermediate terminal and an output terminal (S) designed to be connected to a capacitive load, and which includes: a first negative gain transconductance amplifier (2) connected via open loop between the intermediate terminal and the output terminal; a second negative gain transconductance amplifier (3) with characteristics that are notably identical to those of the first amplifier, connected via closed loop; its input and output are connected to the intermediate terminal via a resistance (R1).