Abstract: Sigma delta modulators and pipelined (also called subranging) converters are used widely in Analog to Digital converters. In general pipelined converters are preferred where the highest speed of conversion is required and sigma delta converters are preferred for lower speed where a significant level of oversampling is possible. The present application describes a converter having the advantages of both types of converter.

Abstract: In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel so as to provide a sequence of independent outputs available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.

Abstract: This application relates to analog to digital converters, particularly AD convertors of the successive approximation type, and to the reduction of power consumption and/or the size of active devices used in these converters. In particular, an analog to digital converter is disclosed in which an array of switched capacitors is decoupled from a comparator. Preferably, this decoupling is achieved using a small capacitor.

Abstract: Mismatch errors within oversampled analog to digital (ADC) and digital to analog (DAC) data converters limit the overall conversion accuracy. A circuit is provided which interchanges the analog segments within a multibit oversampled converter in a fashion to move the mismatch errors away from the overall converter's passband frequencies and towards other frequencies where they do not interfere with the signal to be converted. The circuit works by minimizing the differences in the signals which control the individual segments. Circuits may be provided for achieving first, second and higher order "shaping" of the mismatch errors. The invention also provides a circuit in which exchange of the analog elements with the DACs of multibit oversampled converters is effected using a circular queue, so moving the mismatch errors to high frequency where they do not interfere with the signal to be converted.

Abstract: A sigma-delta analog to digital converter 1 is disclosed. The digital filter comprises digital integrators (8, 10) for reception of the negative feedback signal of the analog modulator. The digital integrators (8, 10) are connected to replicate processing of the feedback signal by the analog integrators (3, 5). Accordingly, the digital filter and the analog modulator may be reset simultaneously so that there is no time lag between conversion cycles. Thus, single shot operation is achieved.

Abstract: Plasmids carrying one or more genes which confer phage insensitivity upon Streptococcus lactis or Streptococcus lactis subsp. diacetylactis as well as Streptococcus cremoris bacteria in which the insensitivity is not destroyed at temperatures of up to 40.degree. C. are described. DNA fragments are also described which encode phage insensitivity. Such plasmids and DNA fragments are suitable for conferring phage insensitivity upon bacteria or food starter cultures containing bacteria.