Patents Assigned to University College London
  • Patent number: 4362899
    Abstract: A three layer printed circuit board comprises upper and lower layers which provide terminal locations for connection to pins of electrical connectors or electronic components which are to be connected in parallel by conductor tracks of the circuit board. In order to achieve an even distribution of conductor tracks between the layers, only certain terminal locations are connected to respective conductor tracks, the locations of the respective layers being electrically connected by plated-through holes. A conductive layer providing a ground plane is located between the upper and lower layers and has non-conductive areas providing clearance for the plated-through holes. Shield tracks are located between the conductor tracks and are connected to the ground plane by plated-through holes so that they form closed conductive loops providing shielding against capacitative and inductive cross-talk between the conductor tracks.
    Type: Grant
    Filed: October 2, 1980
    Date of Patent: December 7, 1982
    Assignee: University College London
    Inventor: Paul L. Borrill