Patents Assigned to Untied Microelectronics Corp.
  • Patent number: 10475932
    Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Untied Microelectronics Corp.
    Inventors: Shao-Hui Wu, Yu-Cheng Tung
  • Patent number: 8643397
    Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Untied Microelectronics Corp.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung