Abstract: In a data processing system in which a data processing unit has an M-bit address register and is connected via an N-bit address bus with a memory (where N<M<2n), the content of the address register is sent out on the address bus in two stages. Namely, high-order N bits of the address register are sent out first, and low-order N-bits are sent out next. One of the bits of the address register is sent out twice by the first and second sending-out operations. The system includes, in combination, various gates and a multiplexer to accomplish data transfer selectively for both virtual memory and real memory operation.