Patents Assigned to UTAC HEADQUARTERS PTE. LTD.
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Publication number: 20170352555Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.Type: ApplicationFiled: August 10, 2017Publication date: December 7, 2017Applicant: UTAC Headquarters PTE. LTD.Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
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Patent number: 9805955Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.Type: GrantFiled: November 9, 2016Date of Patent: October 31, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
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Patent number: 9773722Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).Type: GrantFiled: May 7, 2015Date of Patent: September 26, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjavasukul
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Patent number: 9741642Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.Type: GrantFiled: February 11, 2016Date of Patent: August 22, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjasukul
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Patent number: 9741619Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: GrantFiled: January 9, 2017Date of Patent: August 22, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: William John Nelson, Nathapong Suthiwongsunthorn, Beng Yeung Ho, Poh Leng Wilson Ong
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Patent number: 9704726Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: September 18, 2015Date of Patent: July 11, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Patent number: 9613877Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: GrantFiled: October 10, 2013Date of Patent: April 4, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, John Ducyao Beleran, Serafin Padilla Pedron, Jr.
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Patent number: 9589875Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: September 9, 2015Date of Patent: March 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Patent number: 9570314Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: GrantFiled: October 13, 2015Date of Patent: February 14, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: William John Nelson, Nathapong Suthiwongsunthorn, Beng Yeung Ho, Poh Leng Wilson Ong
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Patent number: 9564387Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.Type: GrantFiled: July 8, 2015Date of Patent: February 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Antonio Bambalan Dimaano, Jr., Rui Huang
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Patent number: 9520306Abstract: A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.Type: GrantFiled: September 14, 2012Date of Patent: December 13, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Geraldine Tsui Yee Lin, Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
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Patent number: 9508623Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: June 5, 2015Date of Patent: November 29, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Patent number: 9472532Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.Type: GrantFiled: April 3, 2015Date of Patent: October 18, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Antonio Bambalan Dimaano, Jr., Nathapong Suthiwongsunthorn, Yong Bo Yang
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Patent number: 9449900Abstract: A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector bumps of the die after reflowing. In some embodiments, the support features are formed from material that is different from the leadframe, such as by a ball drop process or a plating process. In some embodiments, the support features are formed from the leadframe material, such as by etching. In some embodiments, the support features are covered with a coating material.Type: GrantFiled: July 12, 2010Date of Patent: September 20, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
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Patent number: 9391026Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.Type: GrantFiled: December 4, 2014Date of Patent: July 12, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventor: Chuen Khiang Wang
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Patent number: 9312240Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.Type: GrantFiled: October 23, 2014Date of Patent: April 12, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Kriangsak Sae Le, Chee Kay Chow