Patents Assigned to UTAC - United Test and Assembly Test Center Ltd.
  • Patent number: 7851899
    Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: December 14, 2010
    Assignees: UTAC - United Test and Assembly Test Center Ltd., Infineon Technologies
    Inventors: Fung Leng Chen, Seong Kwang Brandon Kim, Wee Lim Cha, Yi-Sheng Anthony Sun, Wolfgang Hetzel, Jochen Thomas
  • Patent number: 7678610
    Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 16, 2010
    Assignee: UTAC-United Test and Assembly Test Center Ltd.
    Inventors: Chuen Khiang Wang, Hien Boon Tan, Anthony Yi Sheng Sun, Sin Nee Song, Steven Yu Feng Yao, Hua Hong Tan
  • Publication number: 20090194871
    Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.
    Type: Application
    Filed: December 24, 2008
    Publication date: August 6, 2009
    Applicant: UTAC - United Test and Assembly Test Center, Ltd.
    Inventors: Denver Paul C. Castillo, Soon Hua Bryan Tan, Rodel Manalac, Kian Teng Eng, Pang Hup Ong, Soo Pin Chow, Wolfgang Johannes Hetzel, Werner Josef Reiss, Florian Ammer
  • Patent number: 7361995
    Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: April 22, 2008
    Assignees: Xilinx, Inc., UTAC - United Test and Assembly Test Center Ltd.
    Inventors: Kim Yong Goh, Rahul Kapoor, Anthony Yi-Sheng Sun, Desmond Yok Rue Chong, Lan H. Hoang