Abstract: A method for removing extraneous matters from a stainless device is provided. The method includes the steps of (a) providing a container for holding a fluorine-containing neutral solution therein, (b) immersing said stainless device in said fluorine-containing neutral solution to remove said extraneous matters from said stainless device, and (c) heating and swirling said fluorine-containing solution. The fluorine-containing neutral solution is made from neutralizing hydrofluoric acid (HF) with ammonium hydroxide (NH4OH), neutralizing hydrofluoric acid (HF) with ammonium fluoride (NH4F), or dissolving ammonium acid fluoride (NH4F) in a deionized water (DIW).

Abstract: A method of fabricating an unlanded via. A substrate has a metal layer formed thereon and an ARC layer is formed on the metal layer. A liner dielectric layer is formed on the ARC layer and the sidewall of the metal layer, and an insulating material layer is formed on the insulating dielectric layer. The insulating material layer is then etched back, so a surface of the insulating material layer lower than the ARC layer surface is formed. Thereafter, a protective layer is formed on the insulating material layer and the metal layer, in which the protective layer is different from the liner dielectric layer. An IMD layer is formed on the protective layer. Using the liner dielectric layer as an etching stop layer, the IMD layer and the protective layer are patterned, and then the liner dielectric layer on the metal layer is removed, such that an unlanded via opening is formed.

Abstract: An exhaust treatment machine. The exhaust treatment machine has a burning chamber and a wet chamber. Water is injected into the wet chamber by a water inlet at a bottom portion of the wet chamber. At least two rotor blades are installed over the bottom of the wet chamber to generate a vortex flow of the water. Thus, the vortex flow of the water acentrically flushes away the product produced in the burning chamber and removes it via a drainpipe. Furthermore, those clots agglomerated from the powers produced in the burning chamber are fragmented by the rotor blades. The problems of blocking the drainpipe is thus resolved.

Abstract: A method of making dual-gate structure with only three masking steps is provided.

Abstract: A process for ROM coding is described. First, the active device areas and isolation regions are defined on a semiconductor substrate. Then, silicon isotopes (Si.sup.30) are implanted into the active device areas to form isotope regions. Next, the remaining portions of the MOSFET structures are then formed. Next, an interlayer dielectric layer, and a metal layer are sequentially deposited and patterned to finish the basic ROM structure. Upon the receipt of an order, a passivation layer is deposited overlaying the interlayer dielectric layer. Next, a photoresist layer is coated over the passivation layer, and code implant windows are patterned. Finally, neutron irradiation is performed to activate the silicon isotopes into N-type phosphorus ions.

Abstract: A method of manufacturing self-aligned titanium salicide is provided which includes the steps of forming a LOCOS isolation region on a silicon substrate, forming a titanium layer on the surface of the silicon substrate, performing a first two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases to convert the titanium layer into a titanium salicide layer, selectively etching the silicon substrate to remove the titanium layer that has not reacted with the silicon substrate, and performing a second two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases. Each of the two-step rapid thermal anneals include a first pre-heat step and a second anneal step.

Abstract: A gate oxide and a first conducting layer are formed on a substrate, and then the first conducting layer is patterned and a gate in a NMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series. A layer of hard mask is formed. The layer of hard mask and the first conducting layer are patterned and a gate in a PMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series.