Patents Assigned to UTIMACO, INC.
  • Patent number: 11886626
    Abstract: An apparatus that includes a substrate and a first plurality of circuit components mounted on the substrate, which is associated with a protected area. The apparatus includes a connector formed on the substrate to at least partially circumscribe the protected area and a second plurality of circuit components mounted on the substrate to at least partially circumscribe the connector to form a security barrier to physically inhibit a penetration attack into the protected area.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 30, 2024
    Assignee: Utimaco, Inc.
    Inventors: John M. Lewis, Alvin H. Diep
  • Patent number: 11687680
    Abstract: A technique includes providing a security monitor to at least detect a penetration attack on a circuit assembly that contains the security monitor. The technique includes inhibiting success of the penetration attack, including flexibly mounting the security monitor to the circuit assembly to allow the security monitor to move in response to the security monitor being contacted during the penetration attack.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 27, 2023
    Assignee: Utimaco Inc.
    Inventor: John M. Lewis
  • Patent number: 11036892
    Abstract: An apparatus that includes a substrate and a first plurality of circuit components mounted on the substrate, which is associated with a protected area. The apparatus includes a connector formed on the substrate to at least partially circumscribe the protected area and a second plurality of circuit components mounted on the substrate to at least partially circumscribe the connector to form a security barrier to physically inhibit a penetration attack into the protected area.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 15, 2021
    Assignee: UTIMACO INC.
    Inventors: John M. Lewis, Alvin H. Diep
  • Patent number: 10719633
    Abstract: A technique includes providing a security monitor to at least detect a penetration attack on a circuit assembly that contains the security monitor. The technique includes inhibiting success of the penetration attack, including flexibly mounting the security monitor to the circuit assembly to allow the security monitor to move in response to the security monitor being contacted during the penetration attack.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: July 21, 2020
    Assignee: UTIMACO, INC.
    Inventor: John M. Lewis
  • Patent number: 10417459
    Abstract: An apparatus that includes a substrate and a first plurality of circuit components mounted on the substrate, which is associated with a protected area. The apparatus includes a connector formed on the substrate to at least partially circumscribe the protected area and a second plurality of circuit components mounted on the substrate to at least partially circumscribe the connector to form a security barrier to physically inhibit a penetration attack into the protected area.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 17, 2019
    Assignee: UTIMACO, INC.
    Inventors: John M. Lewis, Alvin H. Diep