Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: A radiation shielding system for protecting an integrated circuit package from ionizing radiation is provided for an integrated circuit package which is substantially planar and has a plurality of package leads extending from at least one surface of the package, substantially perpendicular to a surface of the integrated circuit package. The system comprises a base portion comprising shielding material and defining a well for receiving the integrated circuit package. A lid of shielding material is provided for being attached to the base portion to completely encompass the integrated circuit package. The system also includes means for allowing portions of each of the package leads to exit the well when the integrated circuit package is within the well. The means includes insulating material.

Abstract: A search coprocessor card for attachment to a computer system has an interface to a host processor of the computer system and a processor. The processor has memory for its program and data, and is coupled to one or more search engine devices. Each of the search engine devices is in turn coupled to a memory for holding key tables, and is capable of searching the key tables for matching entries.

Abstract: A cell generator for UTMC's gate array library of core logic cells is implemented using Cadence® Relative Object Design (ROD) software. The ROD functions use design rules to create and align ROD objects. Design rules can be specified for different foundries and technologies, or can be altered to special design requirements. ROD user-defined handles are created to facilitate internal routing and to accommodate different UTMC architectures. Hierarchy is used to minimize the ROD code, and a Cadence® SKILL Makefile generates the entire library automatically.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: Annular transistors are positioned with respect to the n-well diffusion region so that the active channels of the transistors are completely within the diffusion region, thereby avoiding the formation of the edges at the boundary between n+ active channel regions and adjacent field oxide region (the bird's beak region), which are susceptible to the effect of the ionizing radiation. The edgeless design of the gate arrays reduces the degradation of the transistors caused by the bird's beak leakage, while allowing for an unmodified commercial process flow for fabrication. An outer annular transistor and one or more inner annular transistors may be provided. The outer transistor may be used as an active transistor in the formation of logic circuits, or may provide isolation for the one or more inner transistors, which may be connected to form logic circuits.

Abstract: A content addressable memory (“CAM”) engine or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory (“RAM”) devices. The CAM engine configures the RAM as content addressable memory, thereby causing the normally location-addressed RAM to function as CAM. The CAM engine thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.

Abstract: Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

Abstract: A radiation shielded integrated circuit device comprises an integrated circuit die and a first layer of shielding material supporting the integrated circuit die. The first layer has a central portion having a first thickness having an area at least as large as the area of the IC die, and an outer portion having a second thickness less than the first thickness. A wall of ceramic material has a first edge connected to the outer portion of the first layer of shielding material. The wall of ceramic material has an inner surface defining, in conjunction with the first layer of shielding material, a well containing the integrated circuit die. A plurality of wire bond pads are supported by the inner surface of the ceramic wall. A plurality of input/output pads are connected to an exterior surface of the ceramic walls. Conducting material extending through the ceramic material connects each of the wire bond pads to a respective one of input/output pads.

Abstract: A P-channel transistor is disclosed having P+ source and drain regions formed in a N− well, which is formed in a P− substrate. A third P+ region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a CMOS “push-pull” output buffer circuit, the P+ well tie prevents undesired current flow from the bus back to the positive voltage supply. This prevents potential damage to the power supply plane and any additional components connected thereto. In another aspect, the N− well has formed therein both a P+ and N+ well tie. Additional switch circuitry is provided which allows for upper level programmability or selection of either one or both of the two well ties, depending upon the ultimate circuit configuration.

Abstract: A method and apparatus for determining the longest prefix match in a content addressable memory. A content addressable memory device comprises an application specific integrated circuit which interfaces between a general microprocessor and a random access memory so as to create an associative memory structure which includes transition nodes, significant nodes and arcs. A table including multiple data structures is created in the random access memory by the device for storing prefixes and associated data in a predetermined manner. The table is manipulated by the device in response to commands such as add data, delete data, and search for data by the microprocessor.

Abstract: A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: A content addressable memory (“CAM”) engine or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory (“RAM”) devices. The CAM engine configures the RAM as content addressable memory, thereby causing the normally location-addressed RAM to function as CAM. The CAM engine thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.

Abstract: A radiation shield for protecting an integrated circuit device from harmful radiation has a high Z shielding material for absorbing radiation. The radiation shield has a planar lower surface in contact with an upper surface of the integrated circuit device. The radiation shield also has a central portion in substantial registration with integrated circuit device. The central portion has a thickness sufficient to absorb harmful radiation. A distal portion is located about the central portion. A transitional portion is located between and connects the central and distal portions. The transitional portion has a minimum thickness, as, measured from the integrated circuit, that is about equal to the thickness of the central portion.

Abstract: A method of forming metallization layers and vias as part of an interconnect structure within an integrated circuit ("IC") is disclosed. The metallization layers and vias are formed of an alloy consisting of tungsten and one or more other materials such as aluminum, gold, copper, cobalt, titanium, molybdenum or platinum. In the alternative, the alloy may include aluminum and exclude tungsten. The alloy that forms the metallization layers and vias is deposited onto the IC substrate using ionized cluster beam ("ICB") apparatus. The IC substrate is an "in-process" IC in that various active devices (e.g., bipolar and/or MOS transistors), resistors and capacitors are formed in the substrate using conventional techniques prior to the ICB deposition of the alloy layers. Intermediate IC substrate processing steps (e.g., patterning and etching to form the vias) may take place in-between ICB deposition steps.

Abstract: A method of forming a recessed electrically-insulating field oxide region in a semiconductor substrate is disclosed.