Abstract: A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: A content addressable memory (“CAM”) engine or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory (“RAM”) devices. The CAM engine configures the RAM as content addressable memory, thereby causing the normally location-addressed RAM to function as CAM. The CAM engine thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.

Abstract: A radiation shield for protecting an integrated circuit device from harmful radiation has a high Z shielding material for absorbing radiation. The radiation shield has a planar lower surface in contact with an upper surface of the integrated circuit device. The radiation shield also has a central portion in substantial registration with integrated circuit device. The central portion has a thickness sufficient to absorb harmful radiation. A distal portion is located about the central portion. A transitional portion is located between and connects the central and distal portions. The transitional portion has a minimum thickness, as, measured from the integrated circuit, that is about equal to the thickness of the central portion.

Abstract: A method of forming metallization layers and vias as part of an interconnect structure within an integrated circuit ("IC") is disclosed. The metallization layers and vias are formed of an alloy consisting of tungsten and one or more other materials such as aluminum, gold, copper, cobalt, titanium, molybdenum or platinum. In the alternative, the alloy may include aluminum and exclude tungsten. The alloy that forms the metallization layers and vias is deposited onto the IC substrate using ionized cluster beam ("ICB") apparatus. The IC substrate is an "in-process" IC in that various active devices (e.g., bipolar and/or MOS transistors), resistors and capacitors are formed in the substrate using conventional techniques prior to the ICB deposition of the alloy layers. Intermediate IC substrate processing steps (e.g., patterning and etching to form the vias) may take place in-between ICB deposition steps.

Abstract: A method is disclosed for forming a buried contact within an integrated circuit ("IC"). Initially, a gate oxide layer is deposited onto a surface of a silicon substrate. A first polysilicon layer is deposited onto the gate oxide layer using an ionized cluster beam ("ICB") technique. The first polysilicon layer and the gate oxide layer are patterned and etched at predetermined locations, exposing the underlying silicon substrate surface at these locations. A small amount of undesirable native oxide grows on the exposed substrate surface. This oxide represents an unwanted impedance, which degrades IC device performance. The ICB machine is then used to deposit a second layer of polysilicon on the silicon substrate, including over the oxide layer regions and over the exposed silicon substrate surface at the predetermined locations. This second polysilicon deposition step breaks up and removes the unwanted native oxide from the silicon substrate.