Abstract: Two IC chips in a multiple-chip module are stacked together on a common lead frame or substrate of a ball-grid array package to save space. The top chip is wire-bonded to the lead frame. The bottom chip is flip-chip bonded to the lead frame, thus allowing more leads. The common substrate of the two chips are connected together by a conductive layer of metal plate, solder or conductive epoxy. The connecting layer may serve as a heat sinking element or a common electrical terminal.

Abstract: A message generation and automatic dialing system is used in conjunction with a telephone for a customer to receive product information and to place an order for the product or service. The product information such as product list and prices are prerecorded in a ROM and broadcast from a speaker, which is acoustically coupled to the telephone. The speaker then automatically generates dialing tones to connect the telephone to the customer service of the product company for the user to place an order of any product.

Abstract: A low power repair circuit for a memory matrix is achieved by using two cross-coupled 2-input CMOS OR-gates to form a precharged flip-flop, using two PMOS as drivers. The first OR-gate has a load device comprising a number of parallel branches, each having an NMOS switch in series with a fuse. There are twice as many branches as there are addresses in the predecoder for the memory matrix. Two such branches correspond to an address signal and its complement. The parallel branches are connected to ground through an enable switch and are pulled-down when the enable switch is closed by an enable signal. The fuses of the branches are cut according the address of the faulty word line. The gates of the NMOS switches in are connected to the addresses of the word line predecoder. The output of the first OR gate is precharged to be high.

Abstract: The electrode of a storage capacitor of a DRAM cell lies diagonally along the memory cell. The diagonal layout makes the length of the capacitor longer than either the x-dimension or the y-dimension of the memory cell, thus increasing the storage capacitance.

Abstract: The frequency of an integrated oscillator is held constant by using temperature compensation to compensate for the component variations due to temperature variations. A voltage controlled oscillator, which has temperature dependent components, is compensated with a temperature dependent control voltage. The frequency of many kinds of oscillators such as a relaxation oscillators and ring oscillators can be held constant when the operating current is held constant. The operating current is often derived from a current source, which is a voltage to current converter with a current equal to the ratio of a control voltage to a resistance. Since semiconductor resistance has a positive temperature coefficient is used to obtain a temperature invariant current source. The positive temperature coefficient is obtained with the difference junction voltage of two forward-biased pn junction voltages. The magnitude can be controlled by junction areas of the two junctions. The magnitude can also be amplified.

Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Abstract: The electrode of a storage capacitor of a DRAM cell lies diagonally along the memory cell. The diagonal layout makes the length of the capacitor longer than either the x-dimension or the y-dimension of the memory cell, thus increasing the storage capacitance.

Abstract: In a "flat cell" read-only memory with a matrix of memory cells, each memory cell is a MOSFET of either a low threshold voltage, which can be turned on when accessed, or a high threshold voltage which cannot be turned on when accessed. Each memory cell is connected between two adjacent columns of local bit lines. These local bit lines are alternately connected to a upper bank selection switch which is connected to a main bit line, and a lower bank selection switch, which is connected to a main virtual ground line. Since these local bit lines are fabricated with diffusion layers which are resistive, the path length, hence the resistance, to access any memory cell in the matrix from the main bit line to the main virtual ground is made the same by this alternate, interdigital local bit line layout. Thus, the access time is made uniform.The layouts of two adjacent banks are mirrored, so that the bank selection switches of two adjacent banks can share a common selection line.

Abstract: The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows of MOSFETs connected in series. Only one of MOSFETs in a row between an adjacent bit line bus and a virtual ground bus is active and controllable by a sub-word line selection signal with other MOSFETs non-conducting and connected between two adjacent sub-bit lines. These active MOSFETs in different rows are connected in series. One of these active MOSFETs is coupled to a main bit line, and another of these active MOSFETs is coupled to a virtual ground. When the active MOSFET is open, the main bit line signal and the virtual signal appear between the corresponding memory cells between these two corresponding sub-bit lines and are sensed. With this structure, the accessed memory cell is coupled between the main bit line and the virtual ground line through a number of series MOSFETs.

Abstract: The polysilicon bottom electrode of a stacked fin structure storage capacitor for a DRAM cell is self-aligned with the buried contact to the diffusion of a MOSFET. A silicon nitride layer and a sacrificial oxide (sac) umbrella overhangs the buried contact. Using the sac oxide as a mask, the silicon nitride layer is undercut until a part of the polysilicon buried contact is exposed. Then another polysilicon layer is deposited to contact the buried contact and to form the bottom electrode of the capacitor. Thus the bottom electrode and the buried contact are self-aligned. Again, using the sac oxide as a mask, the bottom electrode is etched laterally to form fin-shape electrode. Then, the bottom electrode is deposited with a capacitor dielectric and a top electrode to form the storage capacitor.