Abstract: A distributed computer system comprising a plurality of engines where each engine is useable to form a separate, integrated computer system. The distributed computer system is the functional equivalent of the separate, integrated computer system. An engine on a computer chip has mappable I/O pins that provide selective and mappable access to internal chip locations. A mapper is provided on the chip for mapping the I/O pins. One or more chips with mappable pins are employed to form a computer engine.

Abstract: A power conservation system for use in a computer system. The power system has an activity monitor and a plurality of power modes of operation. The activity monitor detects the activity level of the computer system through hardware and/or software. By controlling the power mode of operation in response to the activity of the computer system, the power consumption of the computer system can be controlled.

Abstract: A power conservation system for use in a computer system. The power conservation system has an activity mointor and a plurality of modes of operation. By controlling the power mode of operation in response to the activity of the computer system, the power consumption of the computer system is controlled. Coupling of circuit power and clock signals are used to control power consumption and both hardware and software components may separately or together monitor and control operation.

Abstract: A distributed computer system comprising a plurality of engines where each engine is useable to form a separate, integrated computer system. The distributed computer system is the functional equivalent of the separate, integrated computer system. An engine on a computer chip has mappable I/O pins that provide selective and mappable access to internal chip locations. A mapper is provided on the chip for mapping the I/O pins. One or more chips with mappable pins are employed to form a computer engine.

Abstract: A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

Abstract: A computer system having a power control unit for selection of voltage levels for pluggable cards, such as PCMCIA cards. The computer system includes a primary unit for executing two or more versions of control software (card drivers within the operating system) including a current version of control software. A pluggable PCMCIA card operates with a card voltage and has pins for signalling with a CD signal that the card is plugged into the computer system. The computer includes a power supply for providing at least first and second supply voltages such as 5 V, 3.3 V and x.x V. Power switches select one of the supply voltages as the card voltage. A power control unit controls the power switching unit to select one of the supply voltages. The power control unit includes a voltage select unit operable in response to the current version of the control software for storing a voltage code for specifying the selected one of the supply voltages.

Abstract: A power conservation system in a computer system which includes a processing unit operating under control of an operating system. The computer system generates distinct call functions to the operating system where each call function is either in an active class or an idle class. The power conservation system has a plurality of states of operation including an ON state, a DOZE state, a SLEEP state and an OFF state. An activity monitor monitors the activity of the computer system and generating control signals for selecting one of the state of operation for the computer system. The activity monitor includes a storage for storing a call value for each distinct call function and activity threshold values for the various states of operation. The call values are weighted for the call functions whereby different call functions have a greater or lesser impact on the value of an activity level. The call value for each call function is retrieved when the call function is made to the operating system.

Abstract: Disclosed is a computer having a display controller for controlling a display where the display provides an image with different selectable gray scale levels. The display controller includes a pattern unit for providing modulation patterns. The modulation patterns include patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related. The display controller additionally includes a modulation unit, operable over the sequential frames, for modulating the data values of pixels with the patterns whereby the intensity level of the pixels over the sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.

Abstract: A data processing system including a central processing unit which connects to two or more buses. The buses include a memory bus connected to a main store, and to two or more I/O devices sharing common control for accesses to the main store. Priority of transfers over the memory bus is determined by priority circuit in a two-way priority between the processing unit and the common I/O devices on the memory bus. One common I/O devices is a display unit and the other common I/O device is a direct memory access disk unit. The display is periodically refreshed. Priority is always granted to the display device. Priority is granted to the disk device as a supplement to a access by the display device. The direct memory access device piggybacks on the priority of the display device.